FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES
    12.
    发明申请
    FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES 审中-公开
    在集成电路和结果设备中填充CAVITIES

    公开(公告)号:US20170047248A1

    公开(公告)日:2017-02-16

    申请号:US15340181

    申请日:2016-11-01

    Abstract: A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.

    Abstract translation: 公开了一种能够填充IC器件和所得器件中无空隙或间隙的高纵横比腔的方法。 实施例包括在第一ILD中提供有源区和/或门触点; 在触点的上表面上形成选择性保护帽; 在保护盖的上表面和第一ILD的上表面上形成第二ILD; 在第二ILD上形成硬掩模叠层; 在第二ILD和硬掩模叠层中形成暴露一个或多个保护盖的空腔; 去除叠层中的选择层以减小空腔的深度; 以及用金属层填充空腔,其中一个或多个空腔中的金属层连接到一个或多个暴露的保护盖的上表面。

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