公开(公告)号：US08828887B2

公开(公告)日：2014-09-09

申请号：US13687877

申请日：2012-11-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kai Frohberg ,  Frank Feustel ,  Thomas Werner

IPC: H01L21/31 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/02107 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/7843 ,  H01L29/785

Abstract: In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.

Abstract translation: 在复杂的半导体器件中，通过在对应的晶体管之间提供间隙或应力去耦合区域，可以在紧密堆积的器件区域的相邻晶体管元件之间实现有效的应力去耦合。 例如，可以在应力诱导材料中形成间隙，以便减小紧密间隔的晶体管元件上的应力诱导材料的相互作用。 在一些说明性方面，应力诱导材料可以作为每个单独的晶体管元件的岛来提供。

公开(公告)号：US20130130498A1

公开(公告)日：2013-05-23

申请号：US13718644

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Frank Feustel ,  Thomas Werner ,  Michael Grillberger ,  Kai Frohberg

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Generally, the present disclosure is related to various techniques that may be used for forming metallization systems in a highly efficient manner by filling via openings and trenches in a common fill process, while reducing negative effects during the patterning of the via opening and the trenches. One illustrative method disclosed herein includes, among other things, forming a via opening in a first dielectric material of a metallization layer of a semiconductor device. Moreover, a second dielectric material is formed above the first dielectric material, wherein the second dielectric material fills the via opening. Furthermore, the method also includes forming a trench in the second dielectric material so as to connect to the via opening, and filling the trench and the via opening with a metal in a common fill process.

Abstract translation: 通常，本公开涉及可以用于通过在公共填充过程中通过开口和沟槽填充而以高效方式形成金属化系统的各种技术，同时在通孔开口和沟槽的图案化期间减少负面影响。 本文公开的一种说明性方法尤其包括在半导体器件的金属化层的第一介电材料中形成通孔。 此外，第二电介质材料形成在第一电介质材料的上方，其中第二介电材料填充通孔。 此外，该方法还包括在第二电介质材料中形成沟槽，以便连接到通孔开口，并在通用填充工艺中用金属填充沟槽和通孔开口。

公开(公告)号：US20160260794A1

公开(公告)日：2016-09-08

申请号：US14634978

申请日：2015-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Oliver Aubel ,  Frank Feustel ,  Thomas Werner

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L23/5227

Abstract: A method of forming a semiconductor device including an inductor is provided, including forming a first dielectric layer of a first dielectric material over a substrate, removing part of the first dielectric layer to create an opening in the first dielectric layer, filling the opening with a second dielectric layer of a second dielectric material different from the first dielectric material, forming a trench in the second dielectric layer, and filling the trench with a conductive material to form an inductor coil. A semiconductor device is provided that includes a first dielectric layer made of a first dielectric material, a second dielectric layer made of a second dielectric material different from the first dielectric material and embedded in the first dielectric layer and a trench filled with a conductive material and formed in the second dielectric layer, representing at least a part of an inductor coil of the inductor.

Abstract translation: 提供一种形成包括电感器的半导体器件的方法，包括在衬底上形成第一电介质材料的第一电介质层，去除第一电介质层的一部分以在第一电介质层中形成开口，用 第二电介质材料与第一介电材料不同的第二电介质层，在第二介电层中形成沟槽，并用导电材料填充沟槽以形成电感线圈。 提供一种半导体器件，其包括由第一电介质材料制成的第一电介质层，由与第一电介质材料不同并嵌入第一电介质层的第二电介质材料制成的第二电介质层和填充有导电材料的沟槽， 形成在第二电介质层中，代表电感器的电感线圈的至少一部分。

公开(公告)号：US20160240473A1

公开(公告)日：2016-08-18

申请号：US15137740

申请日：2016-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Oliver Aubel ,  Frank Feustel

IPC: H01L23/528 ,  H01L25/065 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

公开(公告)号：US09362239B2

公开(公告)日：2016-06-07

申请号：US14519291

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Oliver Aubel ,  Georg Talut ,  Thomas Werner

IPC: H01L23/52 ,  H01L23/60 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53214 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2224/05006 ,  H01L2224/05546

Abstract: The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.

Abstract translation: 本公开涉及包括布置在多个垂直级上的多条连接线的半导体结构，所述多条连接线至少包括布置在第一垂直级中的第一连接线和布置在第二垂直方向上的第二连接线 与第一垂直水平不同的防水层，以及放置在将第一连接线与第二连接线分隔开的垂直空间的至少一部分中的击穿防止层。

公开(公告)号：US08716126B2

公开(公告)日：2014-05-06

申请号：US13769446

申请日：2013-02-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Peter Baars ,  Frank Feustel

IPC: H01L21/4763

CPC classification number: H01L23/5384 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.

Abstract translation: 本文公开了一种说明性的半导体器件，其包括具有漏极和源极区域以及栅电极结构的晶体管。 所公开的半导体器件还包括形成在第一电介质材料中的接触杆，所述接触杆连接到漏极和源极区域之一并且包括第一导电材料，所述接触棒沿晶体管的宽度方向延伸。 此外，说明性器件还包括形成在第二电介质材料中的导电线，该导电线包括具有沿晶体管的长度方向延伸的顶部宽度的上部，以及具有底部宽度延伸的下部 沿着所述长度方向小于所述上部的顶部宽度，其中所述导电线连接到所述接触杆并包括与所述第一导电材料不同的第二导电材料。