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公开(公告)号:US20230063900A1
公开(公告)日:2023-03-02
申请号:US17524438
申请日:2021-11-11
Applicant: GlobalFoundries U.S. Inc.
Inventor: Man Gu , Jagar Singh , Haiting Wang , Jeffrey Johnson
IPC: H01L29/10 , H01L29/08 , H01L29/66 , H01L29/735 , H01L29/737 , H01L29/06
Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.
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公开(公告)号:US20230062747A1
公开(公告)日:2023-03-02
申请号:US17529002
申请日:2021-11-17
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Man Gu , Haiting Wang , Jagar Singh
IPC: H01L29/10 , H01L29/423 , H01L29/735 , H01L29/66
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes a lateral bipolar junction transistor including an extrinsic base region and a bilayer dielectric spacer on sidewalls of the extrinsic base region, and a p-n junction positioned under the bilayer dielectric spacer between the extrinsic base region and at least an emitter region.
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公开(公告)号:US20230061219A1
公开(公告)日:2023-03-02
申请号:US17509384
申请日:2021-10-25
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Haiting Wang , Alexander Derrickson , Jagar Singh , Vibhor Jain , Andreas Knorr , Alexander Martin , Judson R. Holt , Zhenyu Hu
IPC: H01L29/735 , H01L29/66 , H01L29/08 , H01L29/417 , H01L29/737
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.
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公开(公告)号:US20220285523A1
公开(公告)日:2022-09-08
申请号:US17191886
申请日:2021-03-04
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Arkadiusz Malinowski , Alexander M. Derrickson , Haiting Wang
IPC: H01L29/66 , H01L29/06 , H01L29/78 , H01L21/8234
Abstract: A structure includes a semiconductor fin on a substrate. A first fin transistor (finFET) is on the substrate, and a second finFET is on the substrate adjacent the first finFET. The first finFET and the second finFET include respective pairs of source/drain regions with each including a first dopant of a first polarity. An electrical isolation structure is in the semiconductor fin between one of the source/drain regions of the first finFET and one of the source/drain regions for the second FinFET, the electrical isolation structure including a second dopant of an opposing, second polarity. The electrical isolation structure extends to an upper surface of the semiconductor fin. A related method is also disclosed.
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公开(公告)号:US11437568B2
公开(公告)日:2022-09-06
申请号:US16836434
申请日:2020-03-31
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Yanping Shen , Haiting Wang , Sipeng Gu
Abstract: One illustrative memory cell disclosed herein includes at least one layer of insulating material having a first opening and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer includes a spacer opening. The memory cell also includes a bottom electrode positioned within the spacer opening, a memory state material positioned above an upper surface of the bottom electrode and above an upper surface of the internal sidewall spacer, and a top electrode positioned above the memory state material.
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公开(公告)号:US11342453B2
公开(公告)日:2022-05-24
申请号:US16996010
申请日:2020-08-18
Applicant: GlobalFoundries U.S. Inc.
Inventor: Yanping Shen , Haiting Wang , Zhiqing Li
Abstract: Disclosed is a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a replacement metal gate (RMG) structure that includes a first section, which traverses a semiconductor body at a channel region in a first-type well, and a second section, which is adjacent to the first section and which traverses the semiconductor body at a drain drift region in a second-type well. The RMG structure includes, in both sections, a first-type work function layer and a second-type work function layer on the first-type work function layer. However, the thickness of the first-type work function layer in the first section is greater than the thickness in the second section such that the RMG structure is asymmetric. Thus, threshold voltage (Vt) at the first section is greater than Vt at the second section and the LDMOSFET has a relatively high breakdown voltage (BV). Also disclosed are methods for forming the LDMOSFET.
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公开(公告)号:US20210367060A1
公开(公告)日:2021-11-25
申请号:US17398479
申请日:2021-08-10
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Haiting Wang , Hong Yu , Zhenyu Hu
IPC: H01L29/66 , H01L29/78 , H01L29/06 , H01L21/762 , H01L29/45 , H01L21/285 , H01L29/417
Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.
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18.
公开(公告)号:US11164795B2
公开(公告)日:2021-11-02
申请号:US16828273
申请日:2020-03-24
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Sipeng Gu , Judson Holt , Haiting Wang , Bangun Indajang
IPC: H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/08
Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer.
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公开(公告)号:US20210327872A1
公开(公告)日:2021-10-21
申请号:US16853137
申请日:2020-04-20
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Man Gu , Wang Zheng , Teng-Yin Lin , Haiting Wang , Tung-Hsing Lee
Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.
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20.
公开(公告)号:US20210305103A1
公开(公告)日:2021-09-30
申请号:US16828273
申请日:2020-03-24
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Sipeng Gu , Judson Holt , Haiting Wang , Bangun Indajang
IPC: H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/10
Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer.
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