公开(公告)号：US20170110465A1

公开(公告)日：2017-04-20

申请号：US14884747

申请日：2015-10-15

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping ZHENG ,  Eng Huat TOH ,  Kiok Boone Elgin QUEK ,  Yuan SUN

IPC: H01L27/112 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L27/11206 ,  B82Y10/00 ,  B82Y40/00 ,  H01L23/5252 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  Y10S977/765 ,  Y10S977/888 ,  Y10S977/943

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.

公开(公告)号：US20230076182A1

公开(公告)日：2023-03-09

申请号：US17469227

申请日：2021-09-08

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping ZHENG ,  Eng Huat TOH

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  G01K7/36 ,  G01R33/09 ,  G11C11/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to temperature sensors with programmable magnetic tunnel junction structures and methods of manufacture. A structure includes a resistor material connected in series with a programmable magnetic tunnel junction structure in a Wheatstone bridge configuration.

公开(公告)号：US20180102178A1

公开(公告)日：2018-04-12

申请号：US15838340

申请日：2017-12-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping ZHENG ,  Eng Huat TOH ,  Elgin Kiok Boone QUEK

IPC: G11C17/14 ,  H01L45/00 ,  H01L27/112

CPC classification number: G11C17/14 ,  H01L27/11206 ,  H01L45/04 ,  H01L45/1206 ,  H01L45/146 ,  H01L45/165 ,  H01L45/1675

Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.

公开(公告)号：US20140159114A1

公开(公告)日：2014-06-12

申请号：US13707617

申请日：2012-12-07

Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.

Inventor： Ping ZHENG ,  Eng Huat TOH ,  Yuan SUN

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  G11C16/00 ,  H01L27/11582 ,  H01L29/66477 ,  H01L29/66833 ,  H01L29/7926

Abstract: A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell.

Abstract translation: 公开了一种存储器单元。 存储单元包括设置在基板上的垂直基板。 垂直底座包括顶部和底部端子之间的第一和第二通道。 存储单元还包括围绕第一通道的第一栅极和围绕第二通道的第二栅极。 第一和第二栅极形成存储器单元的全栅三极管。