公开(公告)号：US08203179B2

公开(公告)日：2012-06-19

申请号：US12949558

申请日：2010-11-18

申请人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

发明人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

IPC分类号： H01L29/788

CPC分类号： H01L21/31691 ,  H01L21/28273 ,  H01L21/3142 ,  H01L29/42332 ,  H01L29/7881

摘要： Devices are disclosed, such as those having a memory cell. The memory cell includes an active area formed of a semiconductor material; a first dielectric over the semiconductor material; a second dielectric comprising a material having a perovskite structure over the first dielectric; a third dielectric over the second dielectric; and a gate electrode over the third dielectric.

摘要翻译： 公开了诸如具有存储器单元的器件。 存储单元包括由半导体材料形成的有源区; 半导体材料上的第一电介质; 第二电介质，其包括在所述第一电介质上方具有钙钛矿结构的材料; 在所述第二电介质上的第三电介质; 以及位于第三电介质上的栅电极。

公开(公告)号：US20090045447A1

公开(公告)日：2009-02-19

申请号：US11840485

申请日：2007-08-17

申请人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

发明人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

IPC分类号： H01L29/78 ,  H01L21/316 ,  H01L21/28

CPC分类号： H01L21/31691 ,  H01L21/28273 ,  H01L21/3142 ,  H01L29/42332 ,  H01L29/7881

摘要： Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide with the titanium source material and the strontium source material to form the charge trapping layer on the substrate.

摘要翻译： 公开了方法和装置，例如涉及为例如可以包括闪速存储器单元的存储器件形成电荷阱的那些。 将衬底暴露于钛源材料，锶源材料和能够与钛源材料和锶源材料形成氧化物的氧源材料的时间分离的脉冲，以在衬底上形成电荷捕获层。

公开(公告)号：US09577186B2

公开(公告)日：2017-02-21

申请号：US13488190

申请日：2012-06-04

申请人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L21/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/04 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material. The forming thereof includes etching through the conductive material to form opposing laterally outermost conductive edges of said conductive material in the one planar cross section at the conclusion of said etching which are received laterally outward of the opposing laterally outermost edges of the first conductive electrode in the one planar cross section.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 第一导电电极在一个平面横截面中具有垂直最外表面和在最外表面处的相对的横向最外边缘。 在第一导电电极上形成包含多电阻态金属氧化物的材料。 导电材料沉积在多电阻状态的含金属氧化物的材料上。 包含导电材料的存储单元的第二导电电极被接收在多电阻状态的含金属氧化物的材料上。 其形成包括通过导电材料的蚀刻，以在所述蚀刻结束时在一个平面截面中形成所述导电材料的相对的横向最外面的导电边缘，其在第一导电电极的相对的横向最外边缘的横向外侧接收 一个平面截面。

公开(公告)号：US08415661B2

公开(公告)日：2013-04-09

申请号：US13491165

申请日：2012-06-07

申请人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L29/06

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1683

摘要： Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

摘要翻译： 用于形成包含掺杂的硫族化物材料的存储器存取装置的自对准制造方法。 该方法可用于形成三维堆叠的交叉点存储器阵列。 该方法包括在第一导电电极上形成绝缘材料，图案化绝缘材料以形成暴露第一导电电极的部分的通孔，在绝缘材料的通孔内形成存储器访问装置，并在存储器访问上形成存储元件 设备，其中存储在所述存储器元件中的数据可经由所述存储器访问设备访问。 存储器存取装置由掺杂的硫族化物材料形成，并使用自对准制造方法形成。

公开(公告)号：US08198124B2

公开(公告)日：2012-06-12

申请号：US12652576

申请日：2010-01-05

申请人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L21/00

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1683

摘要： Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

摘要翻译： 用于形成包含掺杂的硫族化物材料的存储器存取装置的自对准制造方法。 该方法可用于形成三维堆叠的交叉点存储器阵列。 该方法包括在第一导电电极上形成绝缘材料，图案化绝缘材料以形成暴露第一导电电极的部分的通孔，在绝缘材料的通孔内形成存储器访问装置，并在存储器访问上形成存储元件 设备，其中存储在所述存储器元件中的数据可经由所述存储器访问设备访问。 存储器存取装置由掺杂的硫族化物材料形成，并使用自对准制造方法形成。

公开(公告)号：US20110165728A1

公开(公告)日：2011-07-07

申请号：US12652576

申请日：2010-01-05

申请人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L21/06

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1683

摘要： Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

摘要翻译： 用于形成包含掺杂的硫族化物材料的存储器存取装置的自对准制造方法。 该方法可用于形成三维堆叠的交叉点存储器阵列。 该方法包括在第一导电电极上形成绝缘材料，图案化绝缘材料以形成暴露第一导电电极的部分的通孔，在绝缘材料的通孔内形成存储器访问装置，并在存储器访问上形成存储元件 设备，其中存储在所述存储器元件中的数据可经由所述存储器访问设备访问。 存储器存取装置由掺杂的硫族化物材料形成，并使用自对准制造方法形成。

公开(公告)号：US20120241714A1

公开(公告)日：2012-09-27

申请号：US13488190

申请日：2012-06-04

申请人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L47/00

CPC分类号： H01L45/04 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material. The forming thereof includes etching through the conductive material to form opposing laterally outermost conductive edges of said conductive material in the one planar cross section at the conclusion of said etching which are received laterally outward of the opposing laterally outermost edges of the first conductive electrode in the one planar cross section.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 第一导电电极在一个平面横截面中具有垂直最外表面和在最外表面处的相对的横向最外边缘。 在第一导电电极上形成包含多电阻态金属氧化物的材料。 导电材料沉积在多电阻状态的含金属氧化物的材料上。 包含导电材料的存储单元的第二导电电极被接收在多电阻状态的含金属氧化物的材料上。 其形成包括通过导电材料的蚀刻，以在所述蚀刻结束时在一个平面截面中形成所述导电材料的相对的横向最外面的导电边缘，其在第一导电电极的相对的横向最外边缘的横向外侧接收 一个平面截面。

公开(公告)号：US08211743B2

公开(公告)日：2012-07-03

申请号：US12114096

申请日：2008-05-02

申请人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L21/00

CPC分类号： H01L45/04 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material. The forming thereof includes etching through the conductive material to form opposing laterally outermost conductive edges of said conductive material in the one planar cross section at the conclusion of said etching which are received laterally outward of the opposing laterally outermost edges of the first conductive electrode in the one planar cross section.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 第一导电电极在一个平面横截面中具有垂直最外表面和在最外表面处的相对的横向最外边缘。 在第一导电电极上形成包含多电阻态金属氧化物的材料。 导电材料沉积在多电阻状态的含金属氧化物的材料上。 包含导电材料的存储单元的第二导电电极被接收在多电阻状态的含金属氧化物的材料上。 其形成包括通过导电材料的蚀刻，以在所述蚀刻结束时在一个平面截面中形成所述导电材料的相对的横向最外面的导电边缘，其在第一导电电极的相对的横向最外边缘的横向外侧接收 一个平面截面。

公开(公告)号：US08114468B2

公开(公告)日：2012-02-14

申请号：US12141559

申请日：2008-06-18

申请人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

发明人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

IPC分类号： B05D5/12 ,  B28B19/00 ,  B29B15/00 ,  C23C18/00 ,  C23C20/00 ,  C23C24/00 ,  C23C26/00 ,  C23C28/00 ,  C23C30/00 ,  H01C17/06 ,  H05K3/00 ,  H01L47/00 ,  H01L29/08 ,  H01L35/24 ,  H01L51/00 ,  H01L29/02 ,  H01L21/00 ,  H01L21/16 ,  H01L21/20 ,  H01L21/36 ,  G11C11/00

CPC分类号： H01L27/101 ,  H01L21/0271 ,  Y10S438/947

摘要： A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

摘要翻译： 形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。 含金属氧化物的材料形成在多条所述一条字线或位线中。 在多个所述一条字线或位线之间提供一系列细长的沟槽。 多个自组装嵌段共聚物线形成在沟槽中的各个内，与沟槽侧壁之间对准并且在沟槽侧壁之间形成。 从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线，以形成包含所述金属氧化物的材料的单独可编程的结，其中字线和位线彼此交叉。

公开(公告)号：US20090317540A1

公开(公告)日：2009-12-24

申请号：US12141559

申请日：2008-06-18

申请人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

发明人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

IPC分类号： B05D5/12

CPC分类号： H01L27/101 ,  H01L21/0271 ,  Y10S438/947

摘要： A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

摘要翻译： 形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。 含金属氧化物的材料形成在多条所述一条字线或位线中。 在多个所述一条字线或位线之间提供一系列细长的沟槽。 多个自组装嵌段共聚物线形成在沟槽中的各个内，与沟槽侧壁之间对准并且在沟槽侧壁之间形成。 从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线，以形成包含所述金属氧化物的材料的单独可编程的结，其中字线和位线彼此交叉。