公开(公告)号：US07851307B2

公开(公告)日：2010-12-14

申请号：US11840485

申请日：2007-08-17

申请人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

发明人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

IPC分类号： H01L21/336

CPC分类号： H01L21/31691 ,  H01L21/28273 ,  H01L21/3142 ,  H01L29/42332 ,  H01L29/7881

摘要： Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide with the titanium source material and the strontium source material to form the charge trapping layer on the substrate.

摘要翻译： 公开了方法和装置，例如涉及为例如可以包括闪速存储器单元的存储器件形成电荷阱的那些。 将衬底暴露于钛源材料，锶源材料和能够与钛源材料和锶源材料形成氧化物的氧源材料的时间分离的脉冲，以在衬底上形成电荷捕获层。

公开(公告)号：US08203179B2

公开(公告)日：2012-06-19

申请号：US12949558

申请日：2010-11-18

申请人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

发明人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

IPC分类号： H01L29/788

CPC分类号： H01L21/31691 ,  H01L21/28273 ,  H01L21/3142 ,  H01L29/42332 ,  H01L29/7881

摘要： Devices are disclosed, such as those having a memory cell. The memory cell includes an active area formed of a semiconductor material; a first dielectric over the semiconductor material; a second dielectric comprising a material having a perovskite structure over the first dielectric; a third dielectric over the second dielectric; and a gate electrode over the third dielectric.

摘要翻译： 公开了诸如具有存储器单元的器件。 存储单元包括由半导体材料形成的有源区; 半导体材料上的第一电介质; 第二电介质，其包括在所述第一电介质上方具有钙钛矿结构的材料; 在所述第二电介质上的第三电介质; 以及位于第三电介质上的栅电极。

公开(公告)号：US20090045447A1

公开(公告)日：2009-02-19

申请号：US11840485

申请日：2007-08-17

申请人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

发明人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

IPC分类号： H01L29/78 ,  H01L21/316 ,  H01L21/28

CPC分类号： H01L21/31691 ,  H01L21/28273 ,  H01L21/3142 ,  H01L29/42332 ,  H01L29/7881

摘要： Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide with the titanium source material and the strontium source material to form the charge trapping layer on the substrate.

摘要翻译： 公开了方法和装置，例如涉及为例如可以包括闪速存储器单元的存储器件形成电荷阱的那些。 将衬底暴露于钛源材料，锶源材料和能够与钛源材料和锶源材料形成氧化物的氧源材料的时间分离的脉冲，以在衬底上形成电荷捕获层。

公开(公告)号：US20110062511A1

公开(公告)日：2011-03-17

申请号：US12949558

申请日：2010-11-18

申请人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

发明人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Bhaskar Srinivasan ,  John Smythe

IPC分类号： H01L29/792 ,  B82Y99/00

CPC分类号： H01L21/31691 ,  H01L21/28273 ,  H01L21/3142 ,  H01L29/42332 ,  H01L29/7881

摘要： Devices are disclosed, such as those having a memory cell. The memory cell includes an active area formed of a semiconductor material; a first dielectric over the semiconductor material; a second dielectric comprising a material having a perovskite structure over the first dielectric; a third dielectric over the second dielectric; and a gate electrode over the third dielectric.

摘要翻译： 公开了诸如具有存储器单元的器件。 存储单元包括由半导体材料形成的有源区; 半导体材料上的第一电介质; 第二电介质，其包括在所述第一电介质上方具有钙钛矿结构的材料; 在所述第二电介质上的第三电介质; 以及位于第三电介质上的栅电极。

公开(公告)号：US08637113B2

公开(公告)日：2014-01-28

申请号：US13354163

申请日：2012-01-19

申请人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

发明人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

IPC分类号： C23C18/00 ,  C23C20/00 ,  C23C28/00 ,  C23C30/00 ,  H01C17/06

CPC分类号： H01L27/101 ,  H01L21/0271 ,  Y10S438/947

摘要： A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

摘要翻译： 形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。 含金属氧化物的材料形成在多条所述一条字线或位线中。 在多个所述一条字线或位线之间提供一系列细长的沟槽。 多个自组装嵌段共聚物线形成在沟槽中的各个内，与沟槽侧壁之间对准并且在沟槽侧壁之间形成。 从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线，以形成包含所述金属氧化物的材料的单独可编程的结，其中字线和位线彼此交叉。

公开(公告)号：US08034655B2

公开(公告)日：2011-10-11

申请号：US12099267

申请日：2008-04-08

申请人： John Smythe ,  Bhaskar Srinivasan ,  Gurtej Sandhu

发明人： John Smythe ,  Bhaskar Srinivasan ,  Gurtej Sandhu

IPC分类号： H01L21/8239

CPC分类号： H01L45/04 ,  G11C11/56 ,  G11C13/00 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 绝缘材料沉积在第一电极上。 在第一电极上形成绝缘材料的开口。 开口包括侧壁和底座。 开口侧壁和基底衬有包含少于填充开口的多电阻态金属氧化物材料的多电阻状态层。 存储单元的第二导电电极形成在多个电阻状态层的横向内侧的开口的内部，该电阻层衬在侧壁上，并且在衬底基底上的多电阻状态层的顶部形成。 考虑了其他方面和实现。

公开(公告)号：US20100003782A1

公开(公告)日：2010-01-07

申请号：US12166604

申请日：2008-07-02

申请人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  Neil Greeley ,  Kunal Parekh

发明人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  Neil Greeley ,  Kunal Parekh

IPC分类号： H01L21/16

CPC分类号： H01L45/1683 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 含金属氧化物的材料形成在第一导电电极上。 蚀刻停止材料沉积在包含金属氧化物的材料上。 导电材料沉积在蚀刻停止材料上。 包含所接收的导电材料的存储单元的第二导电电极形成在蚀刻停止材料上。 这样包括通过导电材料蚀刻以相对于蚀刻停止材料停止并且形成非易失性电阻氧化物存储单元，以包括具有包含金属氧化物的材料和其间的蚀刻停止材料的第一和第二导电电极。 考虑其他实现。

公开(公告)号：US08686411B2

公开(公告)日：2014-04-01

申请号：US13837736

申请日：2013-03-15

申请人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L29/06

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1683

摘要： Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

公开(公告)号：US20120241911A1

公开(公告)日：2012-09-27

申请号：US13491165

申请日：2012-06-07

申请人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L29/24

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1683

摘要： Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

摘要翻译： 用于形成包含掺杂的硫族化物材料的存储器存取装置的自对准制造方法。 该方法可用于形成三维堆叠的交叉点存储器阵列。 该方法包括在第一导电电极上形成绝缘材料，图案化绝缘材料以形成暴露第一导电电极的部分的通孔，在绝缘材料的通孔内形成存储器访问装置，并在存储器访问上形成存储元件 设备，其中存储在所述存储器元件中的数据可经由所述存储器访问设备访问。 存储器存取装置由掺杂的硫族化物材料形成，并使用自对准制造方法形成。

公开(公告)号：US20120122292A1

公开(公告)日：2012-05-17

申请号：US13354163

申请日：2012-01-19

申请人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

发明人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

IPC分类号： H01L21/02

CPC分类号： H01L27/101 ,  H01L21/0271 ,  Y10S438/947

摘要： A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

摘要翻译： 形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。 含金属氧化物的材料形成在多条所述一条字线或位线中。 在多个所述一条字线或位线之间提供一系列细长的沟槽。 多个自组装嵌段共聚物线形成在沟槽中的各个内，与沟槽侧壁之间对准并且在沟槽侧壁之间形成。 从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线，以形成包含所述金属氧化物的材料的单独可编程的结，其中字线和位线彼此交叉。