公开(公告)号：US09947405B2

公开(公告)日：2018-04-17

申请号：US15500075

申请日：2014-11-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Glen E. Montgomery ,  Ning Ge ,  Miao Hu ,  Jianhua Yang

IPC: G11C11/04 ,  G11C13/00 ,  G01J1/00 ,  G06G7/16

CPC classification number: G11C13/0069 ,  G01J1/00 ,  G06G7/16 ,  G11C7/062 ,  G11C7/067 ,  G11C7/1006 ,  G11C11/1673 ,  G11C13/0021 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2013/0088 ,  G11C2213/77

Abstract: A method of obtaining a dot product using a memristive dot product engine with a nulling amplifier includes applying a number of programming voltages to a number of row lines within a memristive crossbar array to change the resistance values of a corresponding number of memristors located at intersections between the row lines and a number of column lines. The method also includes applying a number of reference voltages to the number of the row lines and applying a number of operating voltages to the number of the row lines. The operating voltages represent a corresponding number of vector values. The method also includes determining an array output based on a reference output and an operating output collected from the number of column lines.

公开(公告)号：US20190214085A1

公开(公告)日：2019-07-11

申请号：US16353451

申请日：2019-03-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jianhua Yang ,  Miao Hu ,  John Paul Strachan ,  Ning Ge

IPC: G11C13/00 ,  G06G7/16 ,  G06F3/03

CPC classification number: G11C13/0069 ,  G06F3/03 ,  G06G7/16 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/0064 ,  G11C2213/79

Abstract: A memristive dot-product system for vector processing is described. The memristive dot-product system includes a crossbar array having a number of memory elements. Each memory element includes a memristor. Each memory element includes a transistor. The system also includes a vector input register. The system also includes a vector output register.

公开(公告)号：US10319441B2

公开(公告)日：2019-06-11

申请号：US16220647

申请日：2018-12-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

IPC: G11C13/04 ,  G11C13/00 ,  G06G7/16

Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

公开(公告)号：US20190139605A1

公开(公告)日：2019-05-09

申请号：US16220647

申请日：2018-12-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

IPC: G11C13/00 ,  G06G7/16

Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second sat of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

公开(公告)号：US10249356B2

公开(公告)日：2019-04-02

申请号：US15522344

申请日：2014-10-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  John Paul Strachan ,  Jianhua Yang ,  Miao Hu

IPC: G11C11/24 ,  G11C11/34 ,  G06G7/16

Abstract: A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.

公开(公告)号：US20190066780A1

公开(公告)日：2019-02-28

申请号：US16079998

申请日：2016-02-19

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Miao Hu ,  John Paul Strachan ,  Zhiyong Li ,  R. Stanley Williams

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0028 ,  G06G7/16 ,  G11C11/56 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/77

Abstract: Examples herein relate to linear transformation accelerators. An example linear transformation accelerator may include a crossbar array programmed to calculate a linear transformation. The crossbar array has a plurality of words lines, a plurality of bit lines, and a memory cell coupled between each unique combination of one word line and one bit line, where the memory cells are programmed according to a linear transformation matrix. The plurality of word lines are to receive an input vector, and the plurality of bit lines are to output an output vector representing a linear transformation of the input vector.

公开(公告)号：US10008264B2

公开(公告)日：2018-06-26

申请号：US15521542

申请日：2014-10-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

IPC: G11C13/00 ,  G06F17/16 ,  G06F17/11

CPC classification number: G11C13/0069 ,  G06F17/11 ,  G06F17/16 ,  G06G7/16 ,  G11C7/1006 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/15 ,  G11C2213/77

Abstract: A method of obtaining a dot product includes applying a number of first voltages to a corresponding number of row lines within a memristive cross-bar array to change the resistive values of a corresponding number of memristors located a junctions between the row lines and a number of column lines. The first voltages define a corresponding number of values within a matrix, respectively. The method further includes applying a number of second voltages to a corresponding number of the row lines within the memristive cross-bar array. The second voltages define a corresponding number of vector values. The method further includes collecting the output currents from the column lines. The collected output currents define the dot product.

公开(公告)号：US20170316828A1

公开(公告)日：2017-11-02

申请号：US15522364

申请日：2014-10-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Miao Hu ,  Jianhua Yang ,  John Paul Strachan ,  Ning Ge

IPC: G11C13/00 ,  G06F17/16

CPC classification number: G11C13/0069 ,  G06F17/16 ,  G06G7/16 ,  G11C13/0026 ,  G11C13/004 ,  G11C2213/77

Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.

公开(公告)号：US10970625B2

公开(公告)日：2021-04-06

申请号：US15500073

申请日：2014-11-03

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Miao Hu ,  Jianhua Yang ,  Ning Ge

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A device according to examples of the present disclosure includes a crossbar array including a cell. The cell includes a first resistance switch and a second resistance switch connected in series with the first resistance switch. The first and second resistance switches have different switching characteristics. One of the first and second resistance switches may act as a switch, while the other of the first and second resistance switches may weight the switching behavior of the one that acts as the switch.

公开(公告)号：US10410716B2

公开(公告)日：2019-09-10

申请号：US15570980

申请日：2015-09-25

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Miao Hu ,  Zhiyong Li ,  John Paul Strachan

IPC: G11C13/00 ,  G06G7/16 ,  G11C5/05

Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.