公开(公告)号：US20210213730A1

公开(公告)日：2021-07-15

申请号：US16768125

申请日：2019-07-31

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing NG ,  James Michael GARDNER

IPC: B41J2/045

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signals paths which communicate operating signals to the print component, and a memory component to store memory values associated with the print component. A control circuit to, in response to identifying a sequence of operating signals representing a memory read, provide a first analog signal on the analog pad in parallel with a second analog signal from the print component to provide an analog electrical value on the analog pad representing stored memory values selected by the memory read.

公开(公告)号：US20210162740A1

公开(公告)日：2021-06-03

申请号：US16959077

申请日：2019-04-19

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing NG

IPC: B41J2/045 ,  B41J2/175

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a fire line, a plurality of memory elements, a first switch, and a plurality of second switches. The first switch is electrically coupled between the fire line and a first side of each memory element of the plurality of memory elements. Each second switch is electrically coupled to a second side of a respective memory element of the plurality of memory elements.

公开(公告)号：US20170221566A1

公开(公告)日：2017-08-03

申请号：US15489272

申请日：2017-04-17

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Boon Bing NG ,  Hang Ru GOY

IPC: G11C16/08 ,  H01L29/78 ,  G11C8/08 ,  G11C16/26 ,  H01L29/423 ,  H01L27/11514 ,  G11C16/10

CPC classification number: G11C16/08 ,  G11C8/04 ,  G11C8/08 ,  G11C8/12 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11514 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/7841

Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.