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11.发明申请Signal processing circuit, low-voltage signal generator and image display incorporating the same 有权信号处理电路，低压信号发生器和包含其的图像显示公开(公告)号：US20080150924A1
公开(公告)日：2008-06-26
申请号：US12071529
申请日：2008-02-21
申请人： Hidehiko Yamashita , Hajime Washio , Yasushi Kubota , Graham Andrew Cairns , Michael James Brownlow
发明人： Hidehiko Yamashita , Hajime Washio , Yasushi Kubota , Graham Andrew Cairns , Michael James Brownlow
IPC分类号： G06F3/038 , H03K19/0175
CPC分类号： G09G3/3688 , G09G3/20 , G09G2310/0289 , G09G2330/021
摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。
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12.发明授权Signal processing circuit, low-voltage signal generator, and image display incorporating the same 有权信号处理电路，低电压信号发生器和包含其的图像显示器公开(公告)号：US07358950B2
公开(公告)日：2008-04-15
申请号：US10145905
申请日：2002-05-16
申请人： Hidehiko Yamashita , Hajime Washio , Yasushi Kubota , Graham Andrew Cairns , Michael James Brownlow
发明人： Hidehiko Yamashita , Hajime Washio , Yasushi Kubota , Graham Andrew Cairns , Michael James Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/20 , G09G2310/0289 , G09G2330/021
摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。
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公开(公告)号：US06359491B1
公开(公告)日：2002-03-19
申请号：US09567757
申请日：2000-05-10
IPC分类号： H03L500
CPC分类号： H03K19/018571
摘要： A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gates of the transistors T1 and T2 receive a shifted version of the direct input signal IN from a source-follower comprising the transistors T3 and T4.
摘要翻译： 电压电平移位器包括连接在电源线vdd和反相输入端IN之间的互补晶体管T1，T2。 晶体管T1和T2的栅极从包括晶体管T3和T4的源极跟随器接收直接输入信号IN的偏移形式。
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14.发明授权Signal processing circuit, low-voltage signal generator and image display incorporating the same 有权信号处理电路，低压信号发生器和包含其的图像显示公开(公告)号：US07978169B2
公开(公告)日：2011-07-12
申请号：US12071529
申请日：2008-02-21
申请人： Hidehiko Yamashita , Hajime Washio , Yasushi Kubota , Graham Andrew Cairns , Michael James Brownlow
发明人： Hidehiko Yamashita , Hajime Washio , Yasushi Kubota , Graham Andrew Cairns , Michael James Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/20 , G09G2310/0289 , G09G2330/021
摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。
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公开(公告)号：US06617878B2
公开(公告)日：2003-09-09
申请号：US10216347
申请日：2002-08-09
IPC分类号： H03K190175
CPC分类号： H03K3/356113
摘要： A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.
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公开(公告)号：US06556162B2
公开(公告)日：2003-04-29
申请号：US09847661
申请日：2001-05-02
申请人： Michael James Brownlow , Graham Andrew Cairns , Catherine Rosinda Marie Armida Dachs , Hidehiko Yamashita , Yasushi Kubota , Hajime Washio
发明人： Michael James Brownlow , Graham Andrew Cairns , Catherine Rosinda Marie Armida Dachs , Hidehiko Yamashita , Yasushi Kubota , Hajime Washio
IPC分类号： H03M166
CPC分类号： H03M1/682 , G09G3/3688 , G09G2310/0248 , G09G2310/027 , H03M1/687 , H03M1/765 , H03M1/804
摘要： A digital-to-analog converter includes a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit including switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during the precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.
摘要翻译： 数模转换器包括第一转换器级1，用于通过选择合适的低阻抗参考电压将k位输入信号的m个最高有效位转换为上限和下限电压极限VL和VH。 第二转换器级2在由电压限制VL和VH限定的电压范围内执行k位输入的n个最低有效位的线性转换。 包括开关SW1和SW2的预充电电路从负载CLOAD断开级2，负载CLOAD在预充电阶段期间被充电到电压极限VL。 负载随后与电压限制VL断开并连接到级2的输出，以完成负载CLOAD到转换器输出电压的充电。
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公开(公告)号：US06476637B1
公开(公告)日：2002-11-05
申请号：US09568892
申请日：2000-05-11
IPC分类号： H03K190175
CPC分类号： H03K3/356113
摘要： A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.
摘要翻译： 电压电平移位器包括交叉耦合源跟随器形式的输入级和放大器AMP形式的输出级，其可以具有单端或差分输入。 源极跟随器包括晶体管M1和M2以及晶体管M3和M4。 差分输入IN和！IN连接到晶体管M2和M4的栅极。 从晶体管M3的漏极和晶体管M4的源极连接的节点B向晶体管M1的栅极提供偏置电压。 类似地，偏置电压从晶体管M1的漏极和晶体管M2的源极连接到的节点A提供给晶体管M3的栅极。
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公开(公告)号：US06262598B1
公开(公告)日：2001-07-17
申请号：US09517984
申请日：2000-03-03
IPC分类号： H03K190175
CPC分类号： G11C7/062 , H03K19/018521 , H03K19/018528 , H03K19/01855
摘要： A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gate of the transistor T1 is connected to a direct signal input IN whereas the gate of the transistor T2 receives a shifted version of the direct input signal from a source-follower comprising the transistors T3 and T4. The level shifter may also be embodied as a differential cross-coupled sense amplifier with the sources of the drain load transistors being crossed coupled to the differential inputs.
摘要翻译： 电压电平移位器包括连接在电源线vdd和反相输入端IN之间的互补晶体管T1，T2。 晶体管T1的栅极连接到直接信号输入IN，而晶体管T2的栅极接收来自包括晶体管T3和T4的源极跟随器的直接输入信号的偏移版本。 电平移位器还可以被实现为差分交叉耦合读出放大器，其中漏极负载晶体管的源极与差分输入交叉耦合。
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公开(公告)号：US06952244B2
公开(公告)日：2005-10-04
申请号：US10081917
申请日：2002-02-20
申请人： Graham Andrew Cairns , Catherine Rosinda Marie Armida Dachs , Michael James Brownlow , Yasuyoshi Kaise
发明人： Graham Andrew Cairns , Catherine Rosinda Marie Armida Dachs , Michael James Brownlow , Yasuyoshi Kaise
IPC分类号： G02F1/1368 , G02F1/1362 , G09F9/30 , G09F9/35 , G09G3/20 , G09G3/36 , H01L21/336 , H01L29/786 , G02F1/136 , H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/20
CPC分类号： G02F1/136213 , G02F2001/136245 , G09G3/3648 , G09G2300/0809
摘要： An active matrix devise comprises an array of picture elements. Each picture element has an image element, such as an LCD cell (11) connected to a first storage capacitor 12 and arranged to be connected to a data line 4 by an thin film transistor 10 when activated by a scan signal on a scan line 6. A second storage capacitor 21 can be connected across the first capacitor 12 by means of another thin film transistor 20 when desired so as to increase the storage capacitance at the pixel.
摘要翻译： 有源矩阵设计包括一系列图像元素。 每个像素具有诸如连接到第一存储电容器12的LCD单元（11）的图像元件，并且被布置成当由扫描线6上的扫描信号激活时由薄膜晶体管10连接到数据线4 。 当需要时，第二存储电容器21可以通过另一薄膜晶体管20跨越第一电容器12连接，以增加像素处的存储电容。
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公开(公告)号：US08354990B2
公开(公告)日：2013-01-15
申请号：US12087870
申请日：2007-01-29
申请人： Gareth John , Patrick Zebedee , Michael James Brownlow , Tim Gasser , Jeremy Lock , Graham Andrew Cairns , Jaganath Rajendra , Harry Garth Walton
发明人： Gareth John , Patrick Zebedee , Michael James Brownlow , Tim Gasser , Jeremy Lock , Graham Andrew Cairns , Jaganath Rajendra , Harry Garth Walton
IPC分类号： G09G3/36
CPC分类号： H03K17/063 , G09G3/3688 , G09G2310/027 , G09G2310/0286 , G09G2310/0289 , G11C19/184
摘要： In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.
摘要翻译： 在本发明的一个实施例中，驱动电路包括：连接在第一电压源和第二电压源之间的逻辑块，以及包括多个采样电路的采样器。 每个采样电路用于在使用中对输入数据信号进行采样，并将电压输出到相应的输出。 驱动电路还包括具有多个升压电路的升压电路，每个升压电路与相应的一个采样电路相关联，并且在使用中产生升压电压信号并将升压电压信号提供给相应的采样电路 。 每个升压电路连接在第一电压源和第二电压源之间。 逻辑块可以是但不限于移位寄存器。
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