公开(公告)号：US07487369B1

公开(公告)日：2009-02-03

申请号：US09562071

申请日：2000-05-01

申请人： Mayank Gupta ,  Edward T. Pak ,  Javier Villagomez ,  Peter H. Voss

发明人： Mayank Gupta ,  Edward T. Pak ,  Javier Villagomez ,  Peter H. Voss

IPC分类号： G06F1/32 ,  G06F12/00

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  G06F12/0802 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

摘要： The invention provides a cache architecture that selectively powered-up a portion of data array in a pipelined cache architecture. A tag array is first powered-up, but the data array is not powered-up during this time, to determine whether there is a tag hit from the decoded index address comparing to the tag compare data. If there is a tag hit, during a later time, a data array is then powered-up at that time to enable a cache line which corresponds with the tag hit for placing onto a data bus. The power consumed by the tag represents a fraction of the power consumed by the data array. A significant power is conserved during the time in which the tag array is assessing whether a tag hit occurs while the data array is not powered-on at this point.

摘要翻译： 本发明提供一种高速缓存架构，其选择性地加电流水线高速缓存结构中的数据阵列的一部分。 标签阵列首先被加电，但在此期间数据阵列未上电，以确定与标签比较数据相比，是否存在来自解码的索引地址的标签命中。 如果有一个标签命中，在稍后的时间内，数据阵列然后被加电，以启用与标签命中对应的高速缓存行放置在数据总线上。 标签消耗的功率代表数据阵列消耗的功率的一小部分。 在标签阵列评估在此时数据阵列未通电的情况下是否发生标签命中的时间内，节省了大量功率。

公开(公告)号：US5689471A

公开(公告)日：1997-11-18

申请号：US579079

申请日：1995-12-22

申请人： Peter H. Voss ,  Jeffrey L. Linden

发明人： Peter H. Voss ,  Jeffrey L. Linden

IPC分类号： G11C7/14 ,  G11C11/412 ,  G11C11/34

CPC分类号： G11C11/412 ,  G11C7/14

摘要： A dummy cell in a memory array. The memory array includes a storage element for storing one of a first and a second state. The storage element is coupled to circuitry for reading the first or second state from the storage element. The storage element draws a first current when the first state is read by the circuitry. The storage element and circuitry are further coupled to the dummy cell which provides a reference voltage when the circuitry reads the first or second state from the storage element. The dummy cell draws a second current when the circuitry reads the first or second state from the storage element. The second current is not equivalent to the first the first current. In one embodiment, the dummy cell draws approximately half the current that the storage element draws when the circuitry reads the first state from the storage element. In another embodiment, the dummy cell includes a pass transistor which has a width which is approximately half the width of a pass transistor included in the storage element. In still another embodiment, the dummy cell includes a pass transistor which has a length which is approximately twice the length of a pass transistor included in the storage element.

摘要翻译： 存储器阵列中的虚拟单元。 存储器阵列包括用于存储第一状态和第二状态之一的存储元件。 存储元件耦合到用于从存储元件读取第一或第二状态的电路。 当电路读取第一状态时，存储元件绘制第一电流。 当电路从存储元件读取第一或第二状态时，存储元件和电路进一步耦合到虚拟单元，该虚拟单元提供参考电压。 当电路从存储元件读取第一或第二状态时，虚拟单元抽取第二电流。 第二个电流不等于第一个电流。 在一个实施例中，当电路从存储元件读取第一状态时，虚拟单元消耗存储元件吸引的电流的大约一半。 在另一个实施例中，虚设单元包括通过晶体管，其宽度大约是包含在存储元件中的传输晶体管的宽度的一半。 在另一个实施例中，虚设单元包括通过晶体管，其长度大约是包含在存储元件中的通过晶体管的长度的两倍。

公开(公告)号：US5453950A

公开(公告)日：1995-09-26

申请号：US377952

申请日：1995-01-24

申请人： Peter H. Voss ,  Jeffrey L. Linden

发明人： Peter H. Voss ,  Jeffrey L. Linden

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/40

CPC分类号： G11C11/412

摘要： Static random access memory cells (SRAMS) containing five MOS transistors are configured in a memory array such that only three bitlines are required for two cells. A first bitline is coupled to a first side of a first memory cell, and a second bitline is coupled to a first side of the second memory cell. The first and second memory cells share either a common power bitline or a common ground bitline. A control circuit executes a special write operation to write a low logic level on the second side of the memory cells. The control circuit is coupled to the first, second, and third bitlines to generate a first differential voltage across the memory cells that is lower than the operating voltage on the third bitline and to generate a second voltage lower than the operating voltage on the second bitline when storing a low logic level on the second side of the first storage cell. To perform a special write operation on the second storage cell, the control circuit generates the first differential voltage on the third bitline and the second voltage on the first bitline.

摘要翻译： 包含五个MOS晶体管的静态随机存取存储单元（SRAMS）配置在存储器阵列中，使得两个单元仅需要三个位线。 第一位线耦合到第一存储器单元的第一侧，并且第二位线耦合到第二存储器单元的第一侧。 第一和第二存储器单元共享公共功率位线或公共地线。 控制电路执行特殊写入操作以在存储器单元的第二侧上写入低逻辑电平。 控制电路耦合到第一，第二和第三位线以在存储器单元两端产生低于第三位线上的工作电压的第一差分电压，并产生低于第二位线上的工作电压的第二电压 当在第一存储单元的第二侧存储低逻辑电平时。 为了在第二存储单元上执行特殊的写入操作，控制电路在第三位线上产生第一差分电压，并在第一位线上产生第二电压。

公开(公告)号：US4807198A

公开(公告)日：1989-02-21

申请号：US138103

申请日：1987-12-28

申请人： Stephen T. Flannagan ,  Peter H. Voss

发明人： Stephen T. Flannagan ,  Peter H. Voss

IPC分类号： G11C8/06 ,  G11C11/40 ,  G11C13/00

CPC分类号： G11C8/06

摘要： A memory has input buffer circuit which provides high immunity to problems associated with address float while providing high speed for both decoder selection and for transition detection. The input buffer circuit includes a pair of input NOR gates which provides for independent signal paths to a cross-coupled latch. Independent hysteresis circuits are provided to each signal path between the two NOR gates and the cross-coupled latch. This allows for independently selecting the amount of dc margin and hysteresis so that the use of hysteresis does not adversely effect dc margin.

摘要翻译： 存储器具有输入缓冲电路，其对与地址浮动相关的问题提供高抗扰性，同时为解码器选择和转换检测提供高速度。 输入缓冲器电路包括一对输入NOR门，其提供到交叉耦合锁存器的独立信号路径。 独立的滞后电路被提供给两个或非门和交叉耦合的锁存器之间的每个信号路径。 这允许独立地选择直流余量和滞后量，使得滞后的使用不会不利地影响直流裕度。

公开(公告)号：US06400599B1

公开(公告)日：2002-06-04

申请号：US09569543

申请日：2000-05-12

申请人： Peter H. Voss

发明人： Peter H. Voss

IPC分类号： G11C1100

CPC分类号： G06F12/0802 ,  G06F2212/2515

摘要： A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data read into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.

摘要翻译： 包括第一组存储器单元的存储器件，具有预编程状态的第二组存储器单元，以及被配置为访问包括在存储器单元的第一段中的数据的电路。 当从第二组存储器单元读取数据时，该电路包括使能信号，以确定由第二组存储器单元输出的数据是否是在正常操作期间存储的预编程数据或数据。 对于一个实施例，在第一组存储器单元和第二组存储器单元之间以一致的方式执行从存储器单元读取或从其中检索的数据。

公开(公告)号：US06255879B1

公开(公告)日：2001-07-03

申请号：US09562057

申请日：2000-05-01

申请人： Peter H. Voss

发明人： Peter H. Voss

IPC分类号： H03H1126

CPC分类号： H03K5/131 ,  H03K5/133 ,  H03K2005/00058

摘要： The invention is to provide a programmable delay element that can produce a variable delay with many different delay combinations. The invention creates a variable delay through logic gates. A plurality of transmission gates are used to transfer a signal through a plurality of fixed delay lines. Four parallel coupled signal paths, each path having a fixed delay, form the basis of the invention. By selecting a path or by serially adding successive paths, the desired delay of the signal present on the delay line can be achieved.

摘要翻译： 本发明提供一种可编程延迟元件，其可以产生具有许多不同延迟组合的可变延迟。 本发明通过逻辑门产生可变延迟。 多个传输门用于通过多个固定延迟线传送信号。 具有固定延迟的每个路径的四个并行耦合信号路径构成了本发明的基础。 通过选择路径或通过串行地添加连续路径，可以实现延迟线上存在的信号的期望延迟。

公开(公告)号：US06070229A

公开(公告)日：2000-05-30

申请号：US982822

申请日：1997-12-02

申请人： Peter H. Voss

发明人： Peter H. Voss

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F2212/2515

摘要： A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data written into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.

摘要翻译： 包括第一组存储器单元的存储器件，具有预编程状态的第二组存储器单元，以及被配置为访问包括在存储器单元的第一段中的数据的电路。 当从第二组存储器单元读取数据时，该电路包括使能信号，以确定由第二组存储器单元输出的数据是否是在正常操作期间存储的预编程数据或数据。 对于一个实施例，在第一组存储器单元和第二组存储器单元之间以一致的方式执行写入或从存储单元检索的数据。

公开(公告)号：US5245585A

公开(公告)日：1993-09-14

申请号：US604729

申请日：1990-10-22

申请人： Peter H. Voss ,  Cormac M. O'Connell

发明人： Peter H. Voss ,  Cormac M. O'Connell

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C7/1021 ,  G11C7/1033

摘要： In an integrated circuit random access memory internally a xn (n>1) organization is realized, that externally translates to a x1 organization. The n data bits read in parallel are successively and selectively activated and after multiplexing buffered in sequence. Upon buffering but not yet outputting the last data bit of a read address, the next read address may be applied. In this way a multi-address page mode or cross address nibble mode is realized. For writing, a resettable data input delay buffer maintains sufficient margin for both Tdh and Tdv in that any old data is deactivated before new data appears. In this way an equalization pulse no longer is required.

公开(公告)号：US06252819B1

公开(公告)日：2001-06-26

申请号：US09562058

申请日：2000-05-01

申请人： Peter H. Voss

发明人： Peter H. Voss

IPC分类号： G11C800

CPC分类号： G11C8/10

摘要： A reduced line select decoder for a memory array provided comprising a plurality of memory cells arranged at least in one column, a bit line pair connected to the memory cells arranged in one column, a sense amplifier coupled to a bit line pair for differentially amplifying the voltages on the bit line pair in accordance with the voltage on the sense drive line, and a sense amplifier control input responsive to activation of a sense instructing signal to latch data into the sense amplifier and a pair of read/write control signals to select and provide a read/write operation to a selected bit line and connecting to write buffer.

摘要翻译： 一种用于存储器阵列的缩减行选择解码器，包括至少排列成一列的多个存储单元，连接到一列中布置的存储单元的位线对，耦合到位线对的读出放大器，用于差分放大 根据感测驱动线上的电压对位线对上的电压，以及响应于感测指示信号的激活而将数据锁存到读出放大器中的读出放大器控制输入和一对读/写控制信号以选择和 提供对所选位线的读/写操作并连接到写缓冲区。

公开(公告)号：US5923582A

公开(公告)日：1999-07-13

申请号：US868062

申请日：1997-06-03

申请人： Peter H. Voss

发明人： Peter H. Voss

IPC分类号： G11C7/20 ,  G11C11/00

CPC分类号： G11C7/20 ,  G11C11/4125 ,  G11C11/419 ,  G11C17/08

摘要： A memory device including a first block of random access memory (RAM) cells having preprogrammed states, a second block of random access memory cells, and a select circuit configured to reset the first block of RAM cells to their preprogrammed states. When the first block of memory cells are reset to their preprogrammed states, the first block of memory cells may function as ROM memory cells that may be accessed at RAM speeds. The first block of RAM cells may not require additional nonvolatile circuitry in order to perform the ROM function; rather, the first block of RAM cells may each be configured to operate as both a volatile and nonvolatile memory cell using the same cell structure. For one embodiment, the select circuit alters the power applied to the first block of RAM cells to cause these RAM cells to perform a ROM function. Since, the first block of RAM cells may store RAM data when the device operates in RAM mode, and may store preprogrammed ROM data when reset by the select circuit, the first block of RAM cells may have a storage capacity that is greater than the number of RAM cells in the first block.

摘要翻译： 一种存储器件，包括具有预编程状态的随机存取存储器（RAM）单元的第一块，随机存取存储单元的第二块和被配置为将第一块RAM单元复位到其预编程状态的选择电路。 当第一个存储单元块被复位到它们的预编程状态时，第一个存储单元块可以用作可以以RAM速度访问的ROM存储器单元。 为了执行ROM功能，RAM单元的第一块可能不需要额外的非易失性电路; 相反，第一块RAM单元可以被配置为使用相同的单元结构作为易失性和非易失性存储单元来操作。 对于一个实施例，选择电路改变施加到第一块RAM单元的功率，以使这些RAM单元执行ROM功能。 由于第一块RAM单元可以在器件工作在RAM模式时存储RAM数据，并且当由选择电路复位时可以存储预编程的ROM数据，所以第一块RAM单元可能具有大于数字的存储容量 的第一块中的RAM单元。