公开(公告)号：US07698802B2

公开(公告)日：2010-04-20

申请号：US12028439

申请日：2008-02-08

申请人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford, Jr. ,  Vernon R. Norman

发明人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford, Jr. ,  Vernon R. Norman

IPC分类号： G01R31/28

CPC分类号： G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

摘要： A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.

摘要翻译： 一种用于制造芯片上的有源电路的校准装置的方法，包括：提供能够呈现所需电特性的有源电路; 并且提供与有源电路片上的校准机制。 所述校准机构产生控制输出，并且包括被配置为所述有源电路的至少一个段的复制品的被测器件（DUT），并且基于所述被测器件的比较，产生对所述控制输出进行有限调整的测试输出 具有已知电特性的DUT所呈现的电特性。 该方法还包括：将有源电路的每个控制输入端连接到校准机构的相应控制输出。 校准机构的控制输出动态调整施加到有源电路的器件的控制输入，以迫使有源电路呈现所需的电特性。

公开(公告)号：US07149269B2

公开(公告)日：2006-12-12

申请号：US10375286

申请日：2003-02-27

申请人： Hayden C. Cranford, Jr. ,  Vernon R. Norman ,  Martin Schmatz

发明人： Hayden C. Cranford, Jr. ,  Vernon R. Norman ,  Martin Schmatz

IPC分类号： H03D3/24

CPC分类号： H03L7/07 ,  H03L7/091 ,  H03L7/0998 ,  H04L7/0025 ,  H04L7/0337

摘要： A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (φ1a . . . (φna) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (φ1a . . . φna), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (φ1u . . . φnu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (φ1a . . . φna) depending on the sampling phases (φ1u . . . φnu) and said adjusting signal (AS).

摘要翻译： 用于时钟和数据恢复的接收机包括n个采样锁存器（SL1 ... SLn），用于确定n个采样相位（参见图1a）上的参考信号（Ref 2）的n个采样值（SV1 ... SVn）。 （phina）具有采样锁存输入和采样锁存输出，接收器还包括连接到采样锁存器输出的相位位置分析器（5），用于产生调整信号（AS），用于调整采样相位（phi 1 a。 如果采样值（SV1 ... SVn）偏离设定点，则产生采样相位（phi 1 u。。phinu）的相位插值器（9），连接的采样相位调整单元（6） 其相位位置分析器（5）和相位插值器（9）的输入及其对采样锁存器（SL1 ... SLn）的输出被提供用于产生经调整的采样相位（phi1，...） 取决于采样相位（phi 1 u。。phinu）和所述调整信号（AS）。

公开(公告)号：US06977558B2

公开(公告)日：2005-12-20

申请号：US10650396

申请日：2003-08-28

申请人： Hayden C. Cranford, Jr. ,  Stacy J. Garvin ,  Vernon R. Norman ,  Todd M. Rasmus ,  Peter R. Seidel

发明人： Hayden C. Cranford, Jr. ,  Stacy J. Garvin ,  Vernon R. Norman ,  Todd M. Rasmus ,  Peter R. Seidel

IPC分类号： H03L7/08 ,  H03L7/14

CPC分类号： H03L7/08 ,  H03L2207/06

摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

公开(公告)号：US07570071B2

公开(公告)日：2009-08-04

申请号：US12028451

申请日：2008-02-08

申请人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford, Jr. ,  Vernon R. Norman

发明人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford, Jr. ,  Vernon R. Norman

IPC分类号： G01R31/28 ,  G01R35/00 ,  H03K19/003 ,  G06F19/00

CPC分类号： G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

公开(公告)号：US07539473B2

公开(公告)日：2009-05-26

申请号：US11411662

申请日：2006-04-26

申请人： Hayden C. Cranford, Jr. ,  Stacy J. Garvin ,  Vernon R. Norman

发明人： Hayden C. Cranford, Jr. ,  Stacy J. Garvin ,  Vernon R. Norman

IPC分类号： H04B1/18

CPC分类号： H03L7/18 ,  H03L7/0891

摘要： A circuit design, method, and system for tracking VCO calibration without requiring an over-designed divider as in conventional implementation. A filter reset component is added to the inputs of the VCO. A process step is added to the calibration mechanism/process that shorts the filter nodes and thus centers the frequency of the VCO before stepping from one frequency band to the next.

摘要翻译： 用于跟踪VCO校准的电路设计，方法和系统，而不需要如常规实现中的过度设计的分频器。 滤波器复位分量被添加到VCO的输入端。 在校准机构/过程中添加了一个处理步骤，该校准机构/过程使滤波器节点短路，并因此在从一个频带到下一个频带之前将VCO的频率居中。

公开(公告)号：US07368902B2

公开(公告)日：2008-05-06

申请号：US11262101

申请日：2005-10-28

申请人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford, Jr. ,  Vernon R. Norman

发明人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford, Jr. ,  Vernon R. Norman

IPC分类号： G01R35/00 ,  H03K19/003 ,  G06F19/00

CPC分类号： G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

公开(公告)号：US07755420B2

公开(公告)日：2010-07-13

申请号：US12196718

申请日：2008-08-22

申请人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Stephen D. Wyatt

发明人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Stephen D. Wyatt

IPC分类号： H03K5/00

CPC分类号： G05F1/46

摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.

摘要翻译： 用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。 模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。 控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

公开(公告)号：US07721134B2

公开(公告)日：2010-05-18

申请号：US11566576

申请日：2006-12-04

申请人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

发明人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

IPC分类号： H04L25/00 ,  H03D3/24

CPC分类号： G01R31/3171 ,  B82Y25/00 ,  G01R33/093

摘要： A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.

摘要翻译： 提出了一种用于在诊断测试期间确定接收机系统的眼图边缘参数的方法和系统。 接收机前端的电路包括一系列锁存器，XOR门和OR门，它们首先提供数据样本和边缘采样，即在（边沿）时钟的上升沿或下降沿采样的数据，其特征在于相位延迟相对 到数据采样时钟。 接收机还包括用于边缘时钟（边缘）与数据边缘的理想对准的优化电路。 该方法还提供了边缘时钟从理想/锁定位置向左和向右移相以屏蔽数据眼图，以便计算误码率（BER）值。 边缘时钟相对于数据采样时钟的位置决定了计算的BER的水平眼睛开度。

公开(公告)号：US07684478B2

公开(公告)日：2010-03-23

申请号：US11427831

申请日：2006-06-30

申请人： Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

发明人： Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

IPC分类号： H04B17/00 ,  H04L27/06

CPC分类号： G01R31/31711 ,  H04L1/205 ,  H04L1/24

摘要： A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.

摘要翻译： 通过在具有未知周期TS的IC上以嵌入的采样时钟采样，数字化和存储数据信号的电压采样来生成发送数据信号的K个电压样本的序列。 K电压样本相对于K次顺序TB [K]的时基绘制，归一化，所以所有采样都落在用于生成数据信号的数据时钟或单位时间为1的一个周期内。时基是通过估计 采样时钟周期TSE为1 / P的某个倍数，其中P大于K.眼图分析时间抖动，其中只保存抖动的最小值。 TSE递增1 / P，直到TS大于数据时钟周期的一半。 TSE具有最小时间抖动的眼图用于分析数据通道。

公开(公告)号：US07566946B2

公开(公告)日：2009-07-28

申请号：US11865432

申请日：2007-10-01

申请人： Douglas D. Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

发明人： Douglas D. Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

IPC分类号： H01C10/00

CPC分类号： H01L27/0802 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.

摘要翻译： 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。