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11.发明授权System for determining a reference level and evaluating a signal on the basis of the reference level 有权用于确定参考电平并基于参考电平评估信号的系统公开(公告)号：US07362622B2
公开(公告)日：2008-04-22
申请号：US11099222
申请日：2005-04-05
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/1093 , G11C7/14
摘要： A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.
摘要翻译： 电路呈现信号输入，用于基于在信号输入处接收的信号的特性来确定参考电平的装置。 此外，电路还具有用于基于参考电平来评估信号的装置。
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12.发明申请Memory module and memory configuration with stub-free signal lines and distributed capacitive loads 审中-公开内存模块和内存配置，无短信号线和分布式容性负载公开(公告)号：US20060202328A1
公开(公告)日：2006-09-14
申请号：US11431765
申请日：2006-05-10
IPC分类号： H01L23/34
CPC分类号： G11C5/063 , G11C5/04 , H01L2224/16225 , H05K1/14
摘要： In a memory module for a memory configuration having a bus system made up of a plurality of signal lines, each signal line has respectively been produced essentially without any stub continuously from a supplying contact device to a discharging contact device, disposed close to the supplying contact device, in order to increase a maximum data transmission rate within the memory configuration. Between the supplying contact device and the discharging contact device, each of the signal lines is routed in succession at minimum distances via connection elements associated with the signal line on memory chips associated with the signal line.
摘要翻译： 在具有由多个信号线构成的总线系统的存储器配置的存储器模块中，每个信号线分别基本上没有从供电接触装置连续地到达放电接触装置的任何短截线，放电接触装置靠近供电接点 设备，以便在内存配置中增加最大数据传输速率。 在供电接触装置和放电接触装置之间，通过与与信号线相关联的存储器芯片上的信号线相关联的连接元件，以最小距离连续路由每条信号线。
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13.发明授权公开(公告)号：US07009848B2
公开(公告)日：2006-03-07
申请号：US10609873
申请日：2003-06-30
IPC分类号： H01R12/16
CPC分类号： H05K1/14 , H05K2201/045
摘要： Memory modules without signal-conditioning devices (unbuffered, unregistered) are provided in a system by using adapter cards that have signal-conditioning devices and are then operated in the manner of memory modules with signal-conditioning devices (buffered, registered). Systems can thereby be expanded in a very simple manner and can be flexibly adapted according to requirements, and for this purpose only one type (unbuffered, unregistered) of memory module is required.
摘要翻译： 通过使用具有信号调节装置的适配器卡，然后以具有信号调节装置（缓冲，注册）的存储器模块的方式操作，在系统中提供了没有信号调节装置（无缓冲，未注册）的存储器模块。 因此，系统可以以非常简单的方式进行扩展，并且可以根据要求灵活地进行调整，为此，只需要一种类型（无缓冲，未注册）的存储器模块。
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公开(公告)号：US20050044305A1
公开(公告)日：2005-02-24
申请号：US10887019
申请日：2004-07-08
CPC分类号： G11C5/063
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.
摘要翻译： 本发明涉及一种半导体存储器模块，其具有布置在至少一行的多个存储器芯片和至少一个缓冲器芯片，该缓冲器芯片驱动并接收时钟信号，以及将命令和寻址信号存储到存储器芯片以及从存储器芯片传送数据信号 通过模块内的时钟，地址，命令和数据总线，并形成与外部主存储器总线的接口。 半导体存储器模块具有布置在其上的偶数个缓冲器芯片，并且所有存储器芯片至少通过一个信号线类型从信号组连接到两个相应的缓冲器芯片，并且仅剩下两个缓冲器芯片之一 来自该组的信号线。 在读取操作期间，通过其线从一个缓冲芯片到相应的一个存储器芯片的致动信号的电信号传播时间和从该存储器芯片到另一个缓冲器芯片的数据信号的电信号传播时间之和 对于所有存储器芯片是相同的，并且提供用于控制到存储器芯片或从存储器芯片的相应数据写入和读取操作的控制装置，以便以与数据相同的相同方向驱动时钟信号和命令和寻址信号 当数据被写入和读取时通过模块内的总线发送信号。
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15.发明授权Configuration, plug-in mount and contact element for fixing and contacting switching assemblies on a substrate 失效配置，插件安装和接触元件，用于固定和接触基板上的开关组件公开(公告)号：US06918778B2
公开(公告)日：2005-07-19
申请号：US10609871
申请日：2003-06-30
CPC分类号： H01R12/85 , H01R12/87 , H01R12/88 , H01R13/658
摘要： Contact elements of a plug-in mount are connected in an electrically conducting manner to conductive contact zones on a surface of a substrate after the plug-in mount has been loaded with a switching assembly and are electrically isolated from the signal lines in the unloaded state. Therefore, higher clock rates for the signals transmitted on the signal lines are made possible in not completely expanded systems having empty mounting locations.
摘要翻译： 插入式安装座的接触元件在插入式安装件已经装载有开关组件之后以导电方式连接到衬底表面上的导电接触区域，并且在无负载状态下与信号线电隔离 。 因此，在不具有空的安装位置的完全扩展的系统中，可以在信号线上传输的信号的较高的时钟速率成为可能。
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公开(公告)号：US20050078532A1
公开(公告)日：2005-04-14
申请号：US10909205
申请日：2004-07-30
IPC分类号： G11C5/06 , G11C7/22 , G11C11/4076 , G11C7/00
CPC分类号： G11C7/222 , G11C5/063 , G11C7/22 , G11C11/4076
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via a module-internal clock, address, command and data signal bus. The buffer chip forms an interface to an external memory main bus and the memory chips are arranged in at least one row. The memory chips have separate writing and reading clock signal inputs for receiving the clock signals and the clock signal lines are routed in at least one loop, via the memory chips, from the buffer chip to the end of each row and from there back to the buffer chip
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公开(公告)号：US20050036349A1
公开(公告)日：2005-02-17
申请号：US10890934
申请日：2004-07-14
CPC分类号： G11C29/028 , G11C5/063 , G11C29/50012
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.
摘要翻译： 本发明涉及一种半导体存储器模块，该半导体存储器模块具有彼此排成一列的多个存储器芯片。 存储器模块具有模块内部时钟，命令/地址和数据总线，其将时钟信号，命令和地址信号以及数据信号从存储器控制器设备传送到存储器芯片，并将数据信号从存储器芯片传送到存储器控制器设备 。 存储器模块具有各自的时钟，命令/地址和数据信号线。 时钟信号线包括两个差分时钟信号线，它们在其与存储器控制器装置相对的端部通过短路桥断开或彼此连接。 在写入操作期间，存储器芯片将写入数据与从存储器控制器设备运行到时钟信号线的时钟信号同步，并且在读取操作期间，与从该存储器控制器设备反射的时钟信号同步地输出读取数据 开路或短路的时钟信号线。
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公开(公告)号：US20050024963A1
公开(公告)日：2005-02-03
申请号：US10886814
申请日：2004-07-08
IPC分类号： G11C5/06 , G11C7/10 , G11C11/4093 , G11C7/00
CPC分类号： G11C11/4093 , G11C5/063 , G11C7/10
摘要： The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.
摘要翻译： 本发明涉及一种具有至少一个存储器芯片和缓冲芯片的半导体存储器模块，其将时钟，地址和命令信号驱动到存储器芯片，并且经由模块内部驱动数据信号并从存储器芯片接收它们 时钟，地址，命令和数据总线。 缓冲芯片形成与外部存储器主总线的接口。 数据总线和/或时钟，命令和地址总线分别在两端分别连接到缓冲芯片，并且能够被这两端的缓冲芯片驱动。 正在提供和设置控制装置，使得它们在写入和读取期间它们分别匹配数据信号的传播方向以及相应总线上的时钟，命令和地址信号。
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公开(公告)号：US07831797B2
公开(公告)日：2010-11-09
申请号：US11862915
申请日：2007-09-27
申请人： Hermann Ruckerbauer
发明人： Hermann Ruckerbauer
IPC分类号： G06F12/00
CPC分类号： G11C7/1018 , G06F13/1684
摘要： A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.
摘要翻译： 存储器系统在功能上被设计成使得尽管在没有纠错装置的情况下进行操作，但实际提供用于纠错的存储器模块的存储器芯片被同时用于数据传输。 控制装置被配置为接收，存储和传送数据分组到第一和第二组存储器芯片。 将内部分组数据从控制设备传送到存储器进行，使得第一记录被存储在第二组存储器芯片中，并且附加记录被存储在第一组存储器芯片中。 在优选实施例中，在第二组存储器芯片中分配数据，使得与传送到第一组存储器芯片相比，至少一个额外的转移步骤发生到第二组存储器芯片。 在附加传送步骤中，第一组存储器芯片被从接收数据中被掩蔽。
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20.发明授权Method of refreshing data in a storage location based on heat dissipation level and system thereof 有权基于散热水平及其系统刷新存储位置中的数据的方法公开(公告)号：US07768857B2
公开(公告)日：2010-08-03
申请号：US11949639
申请日：2007-12-03
申请人： Hermann Ruckerbauer
发明人： Hermann Ruckerbauer
IPC分类号： G11C7/04
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40626 , G11C2211/4061
摘要： An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate.
摘要翻译： 一种包括存储位置的集成设备，其中存储在所述存储位置中的数据在第一时间段期间以第一预定刷新率重复地刷新。 第一时间段提供第一预定持续时间。 在第一时间段结束之后，数据以第二预定刷新率反复刷新。
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