公开(公告)号：US11532356B2

公开(公告)日：2022-12-20

申请号：US17223435

申请日：2021-04-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

IPC: G11C13/00 ,  G06N3/04 ,  G11C29/52 ,  G06F11/10

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

公开(公告)号：US11475169B2

公开(公告)日：2022-10-18

申请号：US16291094

申请日：2019-03-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Martin Foltin ,  Aalap Tripathy ,  Harvey Edward White, Jr. ,  John Paul Strachan

IPC: G06F21/76 ,  G06F21/55 ,  H04L29/06 ,  H04L9/40

Abstract: Examples described herein relate to a security system consistent with the disclosure. For instance, the security system may comprise a sensor interface bridge connecting a gateway to an input/output (I/O) card, a Field Programmable Gate Array (FPGA) to scan data to detect an anomaly in the data while the data is in the sensor interface bridge, where a learning neural network accelerator Application-Specific Integrated Circuit (ASIC) is integrated with the FPGA and send the data without an anomaly to the gateway.

公开(公告)号：US11294763B2

公开(公告)日：2022-04-05

申请号：US16115100

申请日：2018-08-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Catherine Graves ,  Dejan S. Milojicic ,  Paolo Faraboschi ,  Martin Foltin ,  Sergey Serebryakov

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.

公开(公告)号：US20210036058A1

公开(公告)日：2021-02-04

申请号：US17041382

申请日：2018-04-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Martin Foltin

IPC: H01L27/24 ,  H01L29/161 ,  H01L29/808 ,  H01L21/02 ,  H01L29/66

Abstract: Devices and methods are provided, In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.

公开(公告)号：US20200285779A1

公开(公告)日：2020-09-10

申请号：US16291094

申请日：2019-03-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Martin Foltin ,  Aalap Tripathy ,  Harvey Edward White, JR. ,  John Paul Strachan

IPC: G06F21/76 ,  G06F21/55 ,  H04L29/06

Abstract: Examples described herein relate to a security system consistent with the disclosure. For instance, the security system may comprise a sensor interface bridge connecting a gateway to an input/output (I/O) card, a Field Programmable Gate Array (FPGA) to scan data to detect an anomaly in the data while the data is in the sensor interface bridge, where a learning neural network accelerator Application-Specific Integrated Circuit (ASIC) is integrated with the FPGA and send the data without an anomaly to the gateway.

公开(公告)号：US10735030B2

公开(公告)日：2020-08-04

申请号：US15670802

申请日：2017-08-07

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Harvey Ray ,  Kevin L. Miller ,  Chris Michael Brueggen ,  Martin Foltin

IPC: H03M13/00 ,  H03M13/37 ,  G06F11/10 ,  H03M13/15 ,  H03M13/35

Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.

公开(公告)号：US10275307B2

公开(公告)日：2019-04-30

申请号：US15454813

申请日：2017-03-09

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Gregg B. Lesartre ,  Craig Warner ,  Martin Foltin ,  Chris Michael Brueggen

IPC: G06F11/10 ,  G11C29/52

Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.

公开(公告)号：US10191884B2

公开(公告)日：2019-01-29

申请号：US15108633

申请日：2014-01-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Martin Foltin

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

Abstract: A method for managing a multi-lane serial link is described. The method includes establishing a serial link between a number of integrated circuits across a first number of lanes. The first number of lanes are a subset of a number of available lanes on the serial link. The method also includes selecting to change a transmission state of a second number of lanes. The second number of lanes are a subset of the available lanes. The method also includes changing the transmission state of the second number of lanes while transmitting data on a number of remaining lanes. The method further includes synchronizing the first number of lanes and the second number of lanes.

公开(公告)号：US20180260273A1

公开(公告)日：2018-09-13

申请号：US15454813

申请日：2017-03-09

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Gregg B. Lesartre ,  Craig Warner ,  Martin Foltin ,  Chris Michael Brueggen

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0401 ,  G11C2029/0409

Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.

公开(公告)号：US20180108410A1

公开(公告)日：2018-04-19

申请号：US15566867

申请日：2015-05-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Luke Whitaker ,  Emmanuelle J. Merced Grafals ,  Martin Foltin

IPC: G11C13/00

CPC classification number: G11C13/0064 ,  G11C11/56 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2013/009 ,  G11C2013/0092

Abstract: An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor.