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    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same
    14.
    发明申请
    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same 有权
    具有具有改善的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法

    公开(公告)号：US20080036006A1

    公开(公告)日：2008-02-14

    申请号：US11802281

    申请日：2007-05-22

    申请人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    发明人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    IPC分类号： H01L29/94 ,  H01L21/8238

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

    摘要翻译： 具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。 该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。 在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

    Method of monitoring link performance and diagnosing active link state in ethernet passive optical network
    16.
    发明申请
    Method of monitoring link performance and diagnosing active link state in ethernet passive optical network 有权
    监控链路性能和诊断以太网无源光网络中主动链路状态的方法

    公开(公告)号：US20060221841A1

    公开(公告)日：2006-10-05

    申请号：US11286632

    申请日：2005-11-22

    申请人： Ho Lee ,  Jee Eun ,  Tae Whan Yoo ,  Bong Kim

    发明人： Ho Lee ,  Jee Eun ,  Tae Whan Yoo ,  Bong Kim

    IPC分类号： H04J3/14

    CPC分类号： H04L43/0811 ,  H04L43/0847 ,  H04L43/16

    摘要： Provided is a method of monitoring link performance and diagnosing an active link state without interrupting traffic in an Ethernet passive optical network (EPON) while the link is in the active state. The method of monitoring link performance and diagnosing an active link state without interrupting data flow to logic links which are in active states in the EPON, includes: a) allowing an operator of the EPON to select a link performance monitoring function or a link active state diagnosing function; b-1) if the link performance monitoring function is selected, setting a monitoring cycle timer and periodically transmitting a performance information request frame from a local node to a remote node; b-2) if the remote node receives the performance information request frame, collecting corresponding link performance information and transmitting a response frame from the remote node to the local node in a format which is predetermined in accordance with a corresponding frame format; b-3) if the local node receives the response frame from the remote node, analyzing the performance information of the response frame and determining whether the link performance has deteriorated or if a failure has occurred in the local node; b-4) if the deterioration of the link function or the degree of the failure reaches a predetermined threshold, reporting to an upper layer that a failure has occurred.

    摘要翻译： 提供了一种在链路处于活动状态时监视链路性能和诊断活动链路状态而不中断以太网无源光网络（EPON）中的业务的方法。 监视链路性能和诊断活动链路状态而不中断到EPON中处于活动状态的逻辑链路的数据流的方法包括：a）允许EPON的运营商选择链路性能监视功能或链路活动状态 诊断功能; b-1）如果选择了链路性能监视功能，则设置监视周期定时器并且周期地从本地节点向远程节点发送性能信息请求帧; b-2）如果所述远程节点接收到所述性能信息请求帧，则收集对应的链路性能信息，并以根据对应的帧格式预定的格式从所述远程节点向所述本地节点发送响应帧; b-3）如果本地节点从远程节点接收到响应帧，分析响应帧的性能信息，确定链路性能是否恶化，或者本地节点是否发生故障; b-4）如果链路功能的劣化或故障程度达到预定阈值，则向上层报告发生故障。

    CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same
    17.
    发明申请
    CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same 有权
    具有升高的源极和漏极区域的CMOS半导体器件及其制造方法

    公开(公告)号：US20060131656A1

    公开(公告)日：2006-06-22

    申请号：US11285978

    申请日：2005-11-23

    申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7834 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628

    摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.

    摘要翻译： 提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。 第一和第二栅极图案分别设置成跨越第一和第二有源区域。 第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。 第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。 在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。 设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。 还提供了制造CMOS器件的方法。

    Methods of fabricating a semiconductor device using a selective epitaxial growth technique
    18.
    发明申请
    Methods of fabricating a semiconductor device using a selective epitaxial growth technique 有权
    使用选择性外延生长技术制造半导体器件的方法

    公开(公告)号：US20060088968A1

    公开(公告)日：2006-04-27

    申请号：US11299447

    申请日：2005-12-08

    申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.

    摘要翻译： 使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。 将具有凹部的基板装入反应室。 将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。 选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

    Method of forming MOS transistor having fully silicided metal gate electrode
    20.
    发明申请
    Method of forming MOS transistor having fully silicided metal gate electrode 有权

    公开(公告)号：US20060008961A1

    公开(公告)日：2006-01-12

    申请号：US11158978

    申请日：2005-06-22

    申请人： Seung-Hwan Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee

    发明人： Seung-Hwan Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

    摘要： Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions. Respective desired thicknesses of the gate-reduced pattern and the elevated source and drain regions may be obtained using an etch selectivity between the poly-crystalline semiconductor layer and the single-crystalline semiconductor layer. A silicidation process is applied to the semiconductor substrate where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.