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    Method of fabricating MOS transistor having epitaxial region
    3.
    发明申请
    Method of fabricating MOS transistor having epitaxial region 有权
    制造具有外延区域的MOS晶体管的方法

    公开(公告)号：US20070054457A1

    公开(公告)日：2007-03-08

    申请号：US11517246

    申请日：2006-09-08

    申请人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee

    发明人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

    摘要： Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects. The method of manufacturing a MOS transistor having an epitaxial region may include forming a gate pattern on a semiconductor substrate, forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask, forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask and partially etching a lower portion of sidewalls of the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.

    摘要翻译： 示例实施例涉及制造半导体器件的方法。 其他示例实施例涉及制造具有设置在栅极图案的侧壁的下部中的外延区域的金属氧化物半导体（MOS）晶体管的方法。 提供一种制造具有提高外延生长速率并且可能具有较少缺陷的外延区域的MOS晶体管的方法。 制造具有外延区域的MOS晶体管的方法可以包括在半导体衬底上形成栅极图案，通过使用栅极图案作为离子注入，将第一杂质离子注入到半导体衬底中，形成具有第一损伤分布的第一离子注入区域 通过使用所述栅极图案作为离子注入掩模将所述第二杂质离子注入到所述半导体衬底中，形成具有与所述第一损伤分布相邻的第二损伤分布的第二离子注入区，并部分地蚀刻所述栅极图案的侧壁的下部;以及 在蚀刻的半导体衬底上原位形成外延区域。

    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same
    4.
    发明授权
    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same 有权
    具有具有改善的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法

    公开(公告)号：US08445968B2

    公开(公告)日：2013-05-21

    申请号：US13091327

    申请日：2011-04-21

    申请人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    发明人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    IPC分类号： H01L21/70

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

    摘要翻译： 具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。 该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。 在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

    Semiconductor device including field effect transistor and method of forming the same
    5.
    发明授权
    Semiconductor device including field effect transistor and method of forming the same 有权
    包括场效晶体管的半导体器件及其形成方法

    公开(公告)号：US07791146B2

    公开(公告)日：2010-09-07

    申请号：US11857157

    申请日：2007-09-18

    申请人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Ji-Hye Yi

    发明人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Ji-Hye Yi

    IPC分类号： H01L29/76

    CPC分类号： H01L29/665 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.

    摘要翻译： 半导体器件包括栅极绝缘体和堆叠在衬底上的栅电极，源极/漏极图案填充形成在与栅电极相邻的相对侧的凹陷区域，源极/漏极图案由掺杂有掺杂剂的硅 - 锗构成 和设置在源极/漏极图案上的金属锗硅化物层。 金属锗硅化物层电连接到源极/漏极图案。 此外，与锗源锗排出图案中的锗量和硅量之和的锗量相比，锗量与金锗烷硅化物层中的锗量和硅量之和的比例低。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07728393B2

    公开(公告)日：2010-06-01

    申请号：US11492939

    申请日：2006-07-26

    申请人： Hwa-sung Rhee ,  Tetsuji Ueno ,  Ho Lee

    发明人： Hwa-sung Rhee ,  Tetsuji Ueno ,  Ho Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66636 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

    摘要： A semiconductor device and method of manufacturing the semiconductor device are provided. The semiconductor device may include a semiconductor substrate, a gate insulation layer and a gate electrode, a first spacer, a second spacer, an epitaxial pattern, and/or source/drain regions. The gate insulation layer and the gate electrode may be formed on the semiconductor substrate. The first spacer may be formed on sidewalls of the gate electrode. The second spacer may be formed on sidewalls of the first spacer. The epitaxial pattern may be formed between the second spacer and the semiconductor substrate such that an outside profile of the epitaxial pattern is aligned with an outside profile of the second spacer. The source/drain regions may include primary source/drain regions that are aligned with the first spacer. The primary source/drain regions may be formed in the epitaxial pattern and the semiconductor substrate. The source/drain regions may also include secondary source/drain regions that are aligned with the second spacer and formed in the semiconductor substrate.

    摘要翻译： 提供一种制造半导体器件的半导体器件和方法。 半导体器件可以包括半导体衬底，栅极绝缘层和栅电极，第一间隔物，第二间隔物，外延图案和/或源极/漏极区域。 栅极绝缘层和栅电极可以形成在半导体衬底上。 第一间隔物可以形成在栅电极的侧壁上。 第二间隔件可以形成在第一间隔件的侧壁上。 外延图案可以形成在第二间隔物和半导体衬底之间，使得外延图案的外部轮廓与第二间隔物的外部轮廓对准。 源极/漏极区域可以包括与第一间隔物对准的主要源极/漏极区域。 初级源极/漏极区域可以形成为外延图案和半导体衬底。 源极/漏极区域还可以包括与第二间隔物对准并形成在半导体衬底中的次级源极/漏极区域。

    Transistor and method of manufacturing the same
    8.
    发明授权
    Transistor and method of manufacturing the same 有权
    晶体管及其制造方法

    公开(公告)号：US07601983B2

    公开(公告)日：2009-10-13

    申请号：US11207703

    申请日：2005-08-19

    申请人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee ,  Dong-Suk Shin ,  Seung-Hwan Lee

    发明人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee ,  Dong-Suk Shin ,  Seung-Hwan Lee

    IPC分类号： H01L29/10

    CPC分类号： H01L29/66636 ,  H01L29/045 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

    摘要： A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

    摘要翻译： 晶体管包括具有{100}晶面的第一表面，{100}晶面的第二表面的半导体衬底的高度低于第一表面的第一表面，以及{111}晶体的第三表面 将第一表面连接到第二表面的平面。 在第二表面下形成第一重掺杂杂质区。 栅极结构形成在第一表面上。 在第二表面和第三表面上形成外延层。 在栅极结构的两侧形成第二重掺杂杂质区。 第二重掺杂杂质区域具有{111}晶面的侧面，从而可以防止在杂质区域之间产生的短沟道效应。

    Semiconductor Devices with Stressed Channel Regions and methods Forming the Same
    9.
    发明申请
    Semiconductor Devices with Stressed Channel Regions and methods Forming the Same 审中-公开
    具有强调通道区域和方法的半导体器件形成相同

    公开(公告)号：US20070057320A1

    公开(公告)日：2007-03-15

    申请号：US11426595

    申请日：2006-06-27

    申请人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    发明人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7848 ,  H01L29/66628 ,  H01L29/66636

    摘要： A semiconductor device includes a substrate having a semiconductor channel region therein. A gate electrode is provided on the channel region. A SiGeC stress-inducing region is provided adjacent the channel region. The SiGeC region is configured to form a semiconductor junction with the channel region and induce a net mobility-enhancing stress in a portion of the channel region. The SiGeC region may have a Ge/C atomic ratio of less than about 12. The SiGeC region also has a sufficient concentration of substitutional C atoms therein to induce a net tensile stress in the portion of the channel region, which has a different lattice constant relative to the SiGeC region.

    摘要翻译： 半导体器件包括其中具有半导体沟道区的衬底。 栅电极设置在沟道区上。 在沟道区附近提供SiGeC应力诱导区。 SiGeC区域被配置为与沟道区域形成半导体结，并且在沟道区域的一部分中引起净迁移率增强应力。 SiGeC区域可以具有小于约12的Ge / C原子比.SiGeC区域还具有足够的取代C原子浓度，以在沟道区域中具有不同晶格常数的部分中的净拉伸应力 相对于SiGeC区域。