公开(公告)号：US20080229144A1

公开(公告)日：2008-09-18

申请号：US12131307

申请日：2008-06-02

申请人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

发明人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

IPC分类号： G06F11/00

CPC分类号： G11C29/808

摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

公开(公告)号：US07307911B1

公开(公告)日：2007-12-11

申请号：US11460464

申请日：2006-07-27

申请人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

发明人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： An apparatus for sensing the state of a programmable resistive memory element device includes a latch device is coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg. The latch device is configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg. The fuse and reference resistance legs are further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

摘要翻译： 一种用于感测可编程电阻式存储元件器件的状态的装置包括一个锁存器件耦合到一个熔丝节点和一个参考节点，该熔断器节点包含在一个保险丝支脚内，而该参考节点配置在一个参考电阻支路内。 闩锁装置被配置为检测由于感测电流通过保险丝腿和参考电阻腿而导致在参考节点和熔丝节点之间产生的差分信号。 熔丝和参考电阻支腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流水平。

公开(公告)号：US07093171B2

公开(公告)日：2006-08-15

申请号：US10115348

申请日：2002-04-03

申请人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

发明人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

公开(公告)号：US20060285411A1

公开(公告)日：2006-12-21

申请号：US11160273

申请日：2005-06-16

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C7/00

CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4094

摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

摘要翻译： 具有与正常读取和写入操作交织的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。 在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

公开(公告)号：US07145829B1

公开(公告)日：2006-12-05

申请号：US11160273

申请日：2005-06-16

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： C11C7/00

CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4094

摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

摘要翻译： 具有与正常读取和写入操作交错的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。 在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

公开(公告)号：US20090103390A1

公开(公告)日：2009-04-23

申请号：US11875173

申请日：2007-10-19

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C8/00

CPC分类号： G11C8/16 ,  G11C7/02 ,  G11C7/1075 ,  G11C7/18 ,  G11C11/412

摘要： Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.

摘要翻译： 本发明的实施例提供了双重部分单元的存储器阵列及其设计结构。 存储器阵列具有一对扭曲的写位线和用于每列的一对扭转的读位线。 通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，从而产生共模鼻子并且减小差模噪声。

公开(公告)号：US07885138B2

公开(公告)日：2011-02-08

申请号：US11875173

申请日：2007-10-19

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C8/00

CPC分类号： G11C8/16 ,  G11C7/02 ,  G11C7/1075 ,  G11C7/18 ,  G11C11/412

摘要： Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.

摘要翻译： 本发明的实施例提供了双重部分单元的存储器阵列及其设计结构。 存储器阵列具有一对扭曲的写位线和用于每列的一对扭转的读位线。 通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，从而产生共模鼻子并且减小差模噪声。

公开(公告)号：US06950353B1

公开(公告)日：2005-09-27

申请号：US10906051

申请日：2005-02-01

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C7/00 ,  G11C29/24 ,  G11C29/50

CPC分类号： G11C29/50016 ,  G11C11/401 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/1204

摘要： A memory array includes a true bitline and a complementary bitline and a sense amplifier connected thereto; a row of normal cells with capacitors for data storage and bitline storage capacitors. A row of dummy cells with dummy cell capacitors is also provided. A clock provides wordline drive signals to the normal cells. When operating in the test mode, the clock provides at least one dummy wordline drive signal to the dummy cell switch in response to a testing signal for connecting the dummy cell capacitor to the bitline. A plurality of rows of dummy cells can be employed with various permutations of actuation thereof to provide various levels of capacitance connected to the bitlines in the test mode.

摘要翻译： 存储器阵列包括真位线和互补位线和与其连接的读出放大器; 一排带电容器的正常电池，用于数据存储和位线存储电容。 还提供了具有虚拟电池电容器的一排虚拟电池。 时钟向正常单元提供字线驱动信号。 当在测试模式下操作时，响应于用于将虚拟单元电容器连接到位线的测试信号，时钟向虚拟单元开关提供至少一个虚拟字线驱动信号。 可以采用多排虚拟单元，具有其各种驱动排列，以在测试模式中提供连接到位线的各种电容电平。

公开(公告)号：US06947348B2

公开(公告)日：2005-09-20

申请号：US10604374

申请日：2003-07-15

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C7/00 ,  G11C7/22 ,  G11C8/00 ,  G11C11/24 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/4085 ,  G11C11/409 ,  G11C11/4091 ,  G11C2207/2281

摘要： A method is provided for accessing a storage cell of a dynamic random access memory (DRAM) having an array of gain cells being read accessible by a read wordline and a read bitline, and being write accessible by a write wordline and write bitline separate from said read wordline and read bitline. The method includes activating a read wordline of the array of gain cells to permit signals from a plurality of gain cells coupled to the read wordline to develop on a plurality of corresponding read bitlines coupled to the gain cells. An interlock signal is then generated in the DRAM after activating the read wordline. The read wordline is then deactivated in response to the interlock signal.

摘要翻译： 提供一种用于访问动态随机存取存储器（DRAM）的存储单元的方法，该存储单元具有读取字线和读取位线可读取的增益单元阵列，并且可由写入字线写入和与所述读取字线分开的写入位线 阅读字线并阅读位线。 该方法包括激活增益单元阵列的读取字线以允许耦合到读取字线的多个增益单元的信号在耦合到增益单元的多个对应读取位线上形成。 然后在激活读取字线之后，在DRAM中产生互锁信号。 然后，读取的字线响应于互锁信号被去激活。

公开(公告)号：US07286437B2

公开(公告)日：2007-10-23

申请号：US11160302

申请日：2005-06-17

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C5/063 ,  G11C7/02 ,  G11C8/16 ,  G11C11/4097 ,  G11C11/412 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11898

摘要： A memory array of dual part cells has a pair of twisted write bitlines and a pair of twisted read bitlines for each column. The twist is made by alternating the vertical position of each bitline pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.

摘要翻译： 双部分单元的存储器阵列具有一对扭转写位线和每对列的一对扭转读位线。 通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，结果产生共模鼻子并且减小差模噪声。