公开(公告)号：US08139414B2

公开(公告)日：2012-03-20

申请号：US13091479

申请日：2011-04-21

申请人： Jin-Ki Kim ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  Hong Beom Pyeon

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10

摘要： A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.

摘要翻译： 一种用于编程NAND闪存单元以最小化程序压力同时允许随机页面编程操作的方法。 该方法包括从正偏压的源极线不对称地预充电NAND串，同时位线与NAND串解耦，随后将编程电压施加到所选择的存储器单元，然后应用位线数据。 在非对称预充电和编程电压的施加之后，所有选定的存储单元将被设置为编程禁止状态，因为它们将与它们各自的NAND串中的其它存储单元分离，并且它们的通道将被局部升压到有效的电压 用于禁止编程。 VSS偏置位线将本地提升的通道放电到VSS，从而允许对所选存储单元进行编程。 VDD偏置位线对预充电NAND串不起作用，从而保持所选存储单元的程序禁止状态。

公开(公告)号：US20110317482A1

公开(公告)日：2011-12-29

申请号：US13110399

申请日：2011-05-18

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0071

摘要： A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.

摘要翻译： 一种用于改善子字线响应的方法包括生成由至少一个用户参数确定的可变衬底偏置。 可变衬底偏置被施加到存储器的所选子块中的子字线驱动器。 通过修改子字线驱动器的可变衬底偏置来改变子字线驱动器的跨导，从而最小化与子字线驱动器通信的子字线上的电压干扰。

公开(公告)号：US08060691B2

公开(公告)日：2011-11-15

申请号：US13022166

申请日：2011-02-07

申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4243 ,  G06F13/4247

摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

摘要翻译： 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

公开(公告)号：US20110258366A1

公开(公告)日：2011-10-20

申请号：US13023838

申请日：2011-02-09

申请人： Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G06F12/00

CPC分类号： G11C7/1063 ,  G11C16/06

摘要： Status indication in a system having a plurality of memory devices is disclosed. A memory device in the system includes a plurality of data pins for connection to a data bus. The memory device also includes a status pin for connection to a status line that is independent from the data bus. The memory device also includes first circuitry for generating, upon completion of a memory operation having a first duration, a strobe pulse of a second duration much shorter than the first duration. The strobe pulse provides an indication of the completion of the memory operation. The memory device also includes second circuitry for outputting the strobe pulse onto the status line via the status pin.

摘要翻译： 公开了具有多个存储器件的系统中的状态指示。 系统中的存储器件包括用于连接到数据总线的多个数据引脚。 存储器件还包括用于连接到独立于数据总线的状态线的状态引脚。 存储器件还包括第一电路，用于在完成具有第一持续时间的存储器操作时产生比第一持续时间短得多的第二持续时间的选通脉冲。 选通脉冲提供存储器操作完成的指示。 存储器件还包括用于经由状态引脚将选通脉冲输出到状态线上的第二电路。

公开(公告)号：US07991925B2

公开(公告)日：2011-08-02

申请号：US12025177

申请日：2008-02-04

申请人： Shuji Sumi ,  Hong Beom Pyeon

发明人： Shuji Sumi ,  Hong Beom Pyeon

IPC分类号： G06F3/00

CPC分类号： G06F13/1694 ,  G06F13/4243

摘要： A memory controller is unaware of device types (DTs) of a plurality (N) of series-connected memory devices in an interconnection configuration. Possible DTs include, e.g., random access memories and Flash memories. First, the memory controller sends a specific DT (“don't care”) and an initial number of binary code to the first device of the interconnection configuration and the binary code is propagated through the devices. Each device performs a “+1” calculation regardless of the DT. The last device provides the memory controller with Nד+1” from which the memory controller can obtain the number N of devices in the interconnection configuration. Thereafter, the memory controller sends a search number (SN) of binary code and a search DT for DT matching that propagate through the devices. Each device performs DT match determination of “previous match”, “present match” and “don't care match”. Based on the match determination, the SN and search DT are or not modified. The modified or non-modified SN and DT are propagated through the devices. Such processes are repeated. From the propagated SN and DT and the previously recognized number of the devices, the memory controller can identify the DT of each device in the interconnection configuration.

摘要翻译： 存储器控制器不知道互连配置中的多个（N）个串联存储器件的设备类型（DT）。 可能的DT包括例如随机存取存储器和闪速存储器。 首先，存储器控制器向互连配置的第一设备发送特定的DT（“不关心”）和初始数量的二进制代码，并且通过设备传播二进制代码。 每个设备不管DT是否执行“+1”计算。 最后一个设备为内存控制器提供Nד+1”，内存控制器可以从中获取互连配置中的设备数量N。 此后，存储器控制器发送二进制码的搜索号（SN）和通过设备传播的用于DT匹配的搜索DT。 每个设备执行“前一个匹配”，“当前匹配”和“不关心匹配”的DT匹配确定。 基于匹配确定，SN和搜索DT是否被修改。 经修改或未修改的SN和DT通过设备传播。 重复这些过程。 从传播的SN和DT以及先前识别的设备数量，存储器控制器可以识别互连配置中每个设备的DT。

公开(公告)号：US07952929B2

公开(公告)日：2011-05-31

申请号：US12026825

申请日：2008-02-06

申请人： Jin-Ki Kim ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  Hong Beom Pyeon

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10

摘要： A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.

摘要翻译： 一种用于编程NAND闪存单元以最小化程序压力同时允许随机页面编程操作的方法。 该方法包括从正偏压的源极线不对称地预充电NAND串，同时位线与NAND串解耦，随后将编程电压施加到所选择的存储器单元，然后应用位线数据。 在非对称预充电和编程电压的施加之后，所有选定的存储单元将被设置为编程禁止状态，因为它们将与它们各自的NAND串中的其它存储单元分离，并且它们的通道将被局部升压到有效的电压 用于禁止编程。 VSS偏置位线将本地提升的通道放电到VSS，从而允许对所选存储单元进行编程。 VDD偏置位线对预充电NAND串不起作用，从而保持所选存储单元的程序禁止状态。

公开(公告)号：US20100268874A1

公开(公告)日：2010-10-21

申请号：US12827718

申请日：2010-06-30

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G06F12/16 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F3/0664 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/068 ,  G06F9/4408 ,  G06F12/0868 ,  G06F2212/214 ,  Y02D10/154

摘要： A system, method and machine-readable medium are provided to configure a non-volatile memory (NVM) including a plurality of NVM modules, in a system having a hard disk drive (HDD) and an operating system (O/S). In response to a user selection of a hybrid drive mode for the NVM, the plurality of NVM modules are ranked according to speed performance. Boot portions of the O/S are copied to a highly ranked NVM module, or a plurality of highly ranked NVM modules, and the HDD and the highly ranked NVM modules are assigned as a logical hybrid drive of the computer system. Ranking each of the plurality of NVM modules can include carrying out a speed performance test. This approach can provide hybrid disk performance using conventional hardware, or enhance performance of an existing hybrid drive, while taking into account relative performance of available NVM modules.

摘要翻译： 在具有硬盘驱动器（HDD）和操作系统（O / S）的系统中，提供了一种系统，方法和机器可读介质来配置包括多个NVM模块的非易失性存储器（NVM）。 响应于用户选择NVM的混合驱动模式，根据速度性能对多个NVM模块进行排序。 O / S的引导部分被复制到高排名的NVM模块或多个高排名的NVM模块，并且HDD和高排名的NVM模块被分配为计算机系统的逻辑混合驱动器。 对多个NVM模块中的每一个进行排序可以包括进行速度性能测试。 这种方法可以使用常规硬件提供混合磁盘性能，或提高现有混合驱动器的性能，同时考虑可用的NVM模块的相对性能。

公开(公告)号：US07515471B2

公开(公告)日：2009-04-07

申请号：US11583354

申请日：2006-10-19

申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：US07499361B2

公开(公告)日：2009-03-03

申请号：US11835663

申请日：2007-08-08

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4061

摘要： A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.

摘要翻译： 动态随机存取存储器（DRAM）器件具有逐列的DRAM单元阵列。 阵列的每个DRAM单元与相应列的相应行和位线的字线相连。 通过模式检测器检测进入和退出自刷新模式，并提供自刷新模式信号。 响应于自刷新模式信号产生的振荡电路产生基本时间段。 第一分频器/时间周期乘法器根据与DRAM器件有关的过程变化因素来改变基本时间周期。 第二分频器/时间周期乘法器还根据与DRAM器件有关的温度变化因素来改变改变的时间周期。 在自刷新模式下，存储在DRAM单元中的数据被刷新。 根据这两个因素，DRAM器件执行并实现可变DRAM单元保留时间的可靠的自刷新。

公开(公告)号：US20080181214A1

公开(公告)日：2008-07-31

申请号：US11692452

申请日：2007-03-28

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

IPC分类号： H04L12/56

CPC分类号： G06F13/4243

摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the several interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.

摘要翻译： 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。 根据设备类型匹配确定，DT与所生成或接收的ID组合。 组合的DT和ID作为传送到下一个设备的分组。 在多个互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 参考提供给互连设备的设备类型，依次生成ID。 将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。