公开(公告)号：US08125286B2

公开(公告)日：2012-02-28

申请号：US12923435

申请日：2010-09-21

申请人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

IPC分类号： H03B5/12

CPC分类号： H03L7/0991 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/1534 ,  H03K2005/00071 ,  H03K2005/00293 ,  H03L2207/50

摘要： A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

摘要翻译： 数字控制振荡器（DCO）包括脉冲发生器，用于在触发信号的边沿产生脉冲信号，以及至少一个延迟电路，其被连接以延迟由脉冲发生器产生的脉冲信号。 脉冲发生器被耦合以接收来自至少一个延迟电路的延迟脉冲信号中的一个和使能信号作为触发信号。 数字控制变容二极管（DCV）包括具有栅极，源极，漏极和衬底的晶体管，其中栅极，源极，漏极和衬底中的至少一个被耦合以接收两个或更多个中的一个 电压，其中所述两个或更多个电压中的至少一个不是电源电压或接地。

公开(公告)号：US20090146625A1

公开(公告)日：2009-06-11

申请号：US12111210

申请日：2008-04-29

申请人： Hong-Yi Huang ,  Ru-Jie Wang ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Ru-Jie Wang ,  Yuan-Hua Chu

IPC分类号： G05F1/567

CPC分类号： G05F3/30

摘要： A voltage generating apparatus including a voltage generator and a current splitter is provided. The voltage generator has an output node, and generates a first output voltage from the output node. The first output voltage rises when the temperature rises and the current flowing from the output end of the voltage generator is fixed. And the first output voltage drops when the temperature is fixed and the current flowing from the output node of the voltage generator rises. The current splitter is used for increasing the current flowing through the current splitter when the temperature rises. Therefore, the rise of the first output voltage of the voltage generator will be restrained, and the temperature compensation can be achieved.

摘要翻译： 提供一种包括电压发生器和电流分配器的电压产生装置。 电压发生器具有输出节点，并从输出节点产生第一输出电压。 当温度升高时，第一输出电压升高，并且从电压发生器的输出端流出的电流是固定的。 并且当温度固定并且从电压发生器的输出节点流出的电流升高时，第一输出电压下降。 当温度升高时，电流分流器用于增加流过电流分流器的电流。 因此，电压发生器的第一输出电压的上升将被抑制，并且可以实现温度补偿。

公开(公告)号：US20090141595A1

公开(公告)日：2009-06-04

申请号：US12113955

申请日：2008-05-02

申请人： Hong-Yi Huang ,  Yi-Jui Tsai ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Yi-Jui Tsai ,  Yuan-Hua Chu

IPC分类号： H03K5/135 ,  G04F10/00

CPC分类号： G04F10/005 ,  H03K5/135

摘要： A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase detector includes digital delay components for producing delay outputs according to the counting signals and thereby detecting a pulse input signal. The Vernier detector includes digital delay components for detecting the remainder of the pulse input signal according to the difference between the delay outputs produced by the subtracter.

摘要翻译： 公开了一种包括延迟锁相环，减法器，多相检测器和游标检测器的时间 - 数字转换器装置。 这里的延迟锁相环包括用于产生计数信号的数字延迟部件。 多相检测器包括用于根据计数信号产生延迟输出并由此检测脉冲输入信号的数字延迟分量。 游标检测器包括用于根据由减法器产生的延迟输出之间的差来检测脉冲输入信号的剩余部分的数字延迟分量。

公开(公告)号：US20080143413A1

公开(公告)日：2008-06-19

申请号：US11738523

申请日：2007-04-23

申请人： Hong-Yi Huang ,  Shiun-Dian Jan ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Shiun-Dian Jan ,  Yuan-Hua Chu

IPC分类号： H03H11/26

CPC分类号： H03H11/265

摘要： A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.

摘要翻译： 提供了包括第一反相器，第二反相器，可变电阻单元和可变电容单元的可编程延迟电路。 第一反相器接收正相接收信号，并通过反相输出信号线发送反相输出信号。 第二反相器接收反相接收信号，并通过正相输出信号线发送正相输出信号。 可变电阻单元根据延迟控制代码中的M位调节反相输出信号线和正相输出信号线之间的等效电阻。 可变电容单元根据延迟控制代码中的N位来调节反相输出信号线和正相输出信号线之间的等效电容。

公开(公告)号：US20070030041A1

公开(公告)日：2007-02-08

申请号：US11194628

申请日：2005-08-02

申请人： Hong-Yi Huang ,  Jian-Hong Shen ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Jian-Hong Shen ,  Yuan-Hua Chu

IPC分类号： H03L7/06

CPC分类号： H03L7/16 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00052 ,  H03L7/0812 ,  H03L7/0891

摘要： A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced out jitter. It also increases the linearity of delay time versus control voltage. The circular edge combiner can multiply the input signal at a lower supply voltage. The rise and fall time of output signal are more symmetrical. It also present the multiplication factor of the clock generator can be easy to choose with the increasing of the number of delay elements.

公开(公告)号：US08154318B2

公开(公告)日：2012-04-10

申请号：US12394046

申请日：2009-02-27

申请人： Hong-Yi Huang ,  Ruei-lun Pu ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Ruei-lun Pu ,  Yuan-Hua Chu

IPC分类号： H03K19/003

CPC分类号： H04L25/0278 ,  H04L25/0276 ,  H04L25/0282

摘要： A signal transceiver apparatus suitable for a wired signal transceiver system includes a differential signal transmitter, an impendence matching control module and a signal receiver. The signal transmitter has an output terminal which is connected to a transceiver wire. The signal transmitter includes a first impendence tuner and is used to receive a control signal so as to tune impendence of the first impendence tuner according to the control signal. Moreover, the impendence matching control module generates the control signal according to a compare signal and a lock signal. Besides, the signal receiver generates the lock signal and the compare signal according to a compare result between a current flowing through the first impendence tuner and a reference current.

摘要翻译： 适用于有线信号收发系统的信号收发机装置包括差分信号发射机，阻抗匹配控制模块和信号接收机。 信号发射器具有连接到收发器线的输出端子。 信号发射机包括第一阻抗调谐器，并用于接收控制信号，以根据控制信号调整第一阻抗调谐器的阻抗。 此外，阻抗匹配控制模块根据比较信号和锁定信号产生控制信号。 此外，信号接收器根据流过第一阻抗调谐器的电流与参考电流之间的比较结果产生锁定信号和比较信号。

公开(公告)号：US20110156782A1

公开(公告)日：2011-06-30

申请号：US12871920

申请日：2010-08-31

申请人： Hong-Yi Huang ,  Chih-Yuan Hsu ,  Wei-Sheng Tseng ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Chih-Yuan Hsu ,  Wei-Sheng Tseng ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

IPC分类号： H03L7/06 ,  H03K5/01

CPC分类号： H04B1/69 ,  G06F1/022 ,  H03L7/197

摘要： An onion waveform generator and a spread spectrum clock generator (SSCG) using the same are provided. The onion waveform generator includes a value generation unit and an accumulating unit. The value generation unit outputs a counting value. The accumulating unit accumulates the counting value to output a waveform value. The accumulating unit switches from an increasing mode to a decreasing mode if the waveform value is a third boundary value, and the accumulating unit switches from the decreasing mode to the increasing mode if the waveform value is a fourth boundary value.

摘要翻译： 提供了洋葱波形发生器和使用它的扩频时钟发生器（SSCG）。 洋葱波形发生器包括值生成单元和累积单元。 值产生单元输出计数值。 累加单元积累计数值，输出波形值。 如果波形值是第三边界值，则累加单元从增加模式切换到减小模式，并且如果波形值是第四边界值，则累加单元从递减模式切换到增加模式。

公开(公告)号：US20110150168A1

公开(公告)日：2011-06-23

申请号：US13041437

申请日：2011-03-07

申请人： Wei-Sheng Tseng ,  Hong-Yi Huang ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

发明人： Wei-Sheng Tseng ,  Hong-Yi Huang ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

IPC分类号： H03K21/00

CPC分类号： H03L7/1976 ,  G06F1/08 ,  H03K23/68

摘要： A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.

摘要翻译： 示出了时钟发生器。 上述时钟发生器包括多模式分频器和Δ-Σ调制器。 多模式分频器通过切换其相位进行归档。 多模分频器有效地增加了时钟发生器的工作频率，并且具有半周期分辨率的特性，用于在其频谱扩展时减少输出时钟信号的抖动。 此外，Δ-Σ调制器通过在其中添加几个分量来增加三角形调制的精度并减少量化误差。 因此，时钟发生器可以扩展到可编程时钟发生器。

公开(公告)号：US07924965B2

公开(公告)日：2011-04-12

申请号：US12391263

申请日：2009-02-24

申请人： Wei-Sheng Tseng ,  Hong-Yi Huang ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

发明人： Wei-Sheng Tseng ,  Hong-Yi Huang ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

IPC分类号： H03K21/00

CPC分类号： H03L7/1976 ,  G06F1/08 ,  H03K23/68

摘要： A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.

摘要翻译： 示出了时钟发生器。 上述时钟发生器包括多模式分频器和Δ-Σ调制器。 多模式分频器通过切换其相位进行归档。 多模分频器有效地增加了时钟发生器的工作频率，并且具有半周期分辨率的特性，用于在其频谱扩展时减少输出时钟信号的抖动。 此外，Δ-Σ调制器通过在其中添加几个分量来增加三角形调制的精度并减少量化误差。 因此，时钟发生器可以扩展到可编程时钟发生器。

公开(公告)号：US20100164562A1

公开(公告)日：2010-07-01

申请号：US12391263

申请日：2009-02-24

申请人： Wei-Sheng Tseng ,  Hong-Yi Huang ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

发明人： Wei-Sheng Tseng ,  Hong-Yi Huang ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

IPC分类号： H03B19/06 ,  H03B19/00 ,  H03K3/017 ,  H03L7/06

CPC分类号： H03L7/1976 ,  G06F1/08 ,  H03K23/68

摘要： A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.

摘要翻译： 示出了时钟发生器。 上述时钟发生器包括多模式分频器和Δ-Σ调制器。 多模式分频器通过切换其相位进行归档。 多模分频器有效地增加了时钟发生器的工作频率，并且具有半周期分辨率的特性，用于在其频谱扩展时减少输出时钟信号的抖动。 此外，Δ-Σ调制器通过在其中添加几个分量来增加三角形调制的精度并减少量化误差。 因此，时钟发生器可以扩展到可编程时钟发生器。