公开(公告)号：US20120015493A1

公开(公告)日：2012-01-19

申请号：US13241014

申请日：2011-09-22

Applicant: Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

Inventor： Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/66803

Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 植入操作可以在两个氮化物膜沉积操作之间进行。 第一氮化物膜可以是SiNx或SiCNx，第二氮化物膜是SiCNx。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

公开(公告)号：US06380021B1

公开(公告)日：2002-04-30

申请号：US09597193

申请日：2000-06-20

Applicant: Jyh-Haur Wang ,  Chih-Chiang Wang ,  Hsien-Chin Lin ,  Kuo-Hua Pan ,  Carlos H. Diaz

Inventor： Jyh-Haur Wang ,  Chih-Chiang Wang ,  Hsien-Chin Lin ,  Kuo-Hua Pan ,  Carlos H. Diaz

IPC: H01L218238

CPC classification number: H01L21/823814

Abstract: A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.

Abstract translation: 描述了一种用于在减少短沟道效应的同时形成PMOSFET的超浅结的新方法。 提供半导体衬底晶片，其中存在至少一个NMOS有源区和至少一个PMOS有效区。 栅电极形成在NMOS和PMOS区域中。 将N型源极/漏极延伸部分注入NMOS区域。 将晶片退火，由此驱动n型源极/漏极延伸部分。此后，在PMOS区域中注入p型源极/漏极延伸部分，其中p型源极/漏极延伸部未经历退火步骤。 间隔件形成在NMOS和PMOS栅电极的侧壁上。 源极/漏极区域被注入NMOS和PMOS区域，其中源极/漏极区域与间隔物自对准以完成集成电路器件的形成。

公开(公告)号：US5281492A

公开(公告)日：1994-01-25

申请号：US54603

申请日：1993-04-29

Applicant: Hsien-Chin Lin

Inventor： Hsien-Chin Lin

IPC: H01M2/04 ,  H01M2/12

CPC classification number: H01M2/1217 ,  H01M2/043

Abstract: A cover device for a storage battery includes a sub-cover that includes a flat bottom with a plurality of first vent-holes, a top portion and a connecting wall which interconnects the flat bottom and the top portion to define a space therein. The cover device further includes a plurality of tubes, each of which having n open end which is connected to each of the first vent-holes of the flat bottom and a closed end which is plugged into a respective inlet-hole of a main cover of the storage battery so as to close the inlet-hole, and a second vent-hole which is formed in the sub-cover and which communicates the space in the sub-cover with an exterior of the same.

Abstract translation: 一种用于蓄电池的盖装置包括：副盖，其包括具有多个第一通气孔的平底部，顶部和连接壁，其将平底部和顶部部分互连以限定其中的空间。 盖装置还包括多个管，每个管具有连接到平底部的每个第一通气孔的n个开口端，并且封闭端被插入主盖的相应入口孔中 所述蓄电池用于封闭所述入口孔;以及第二通气孔，其形成在所述副罩中并将所述副罩中的空间与所述副罩的外部连通。

公开(公告)号：US09349657B2

公开(公告)日：2016-05-24

申请号：US13162813

申请日：2011-06-17

Applicant: Sheng-Hsiung Wang ,  Hsien-Chin Lin ,  Yuan-Ching Peng ,  Chia-Pin Lin ,  Fan-Yi Hsu ,  Ya-Jou Hsieh

Inventor： Sheng-Hsiung Wang ,  Hsien-Chin Lin ,  Yuan-Ching Peng ,  Chia-Pin Lin ,  Fan-Yi Hsu ,  Ya-Jou Hsieh

IPC: C23C16/24 ,  H01L21/20 ,  H01L21/36 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/311

CPC classification number: H01L21/823857 ,  H01L21/823842 ,  H01L29/66545

Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.

Abstract translation: 一种用于制造集成电路器件的方法，包括提供具有第一区域和第二区域的衬底。 在第一区域和第二区域中的衬底上形成介电层。 在电介质层上形成牺牲栅极层。 对牺牲栅极层和电介质层进行图案化以在第一和第二区域中形成栅极堆叠。 在第一和第二区域内的栅堆叠内形成ILD层。 去除第一和第二区域中的牺牲栅极层。 在第一区域中的介电层上形成保护膜; 然后除去第二区域中的电介质层。

公开(公告)号：US08426923B2

公开(公告)日：2013-04-23

申请号：US12797382

申请日：2010-06-09

Applicant: Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

Inventor： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

IPC: H01L29/423

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Abstract translation: 公开了一种用于制造多栅极半导体器件的系统和方法。 一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。 去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

公开(公告)号：US09070624B2

公开(公告)日：2015-06-30

申请号：US13328875

申请日：2011-12-16

Applicant: Jian-Hao Chen ,  Chia-Yu Lu ,  Tung-Heng Hsieh ,  Kuo-Feng Yu ,  Chin-Shan Hou ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

Inventor： Jian-Hao Chen ,  Chia-Yu Lu ,  Tung-Heng Hsieh ,  Kuo-Feng Yu ,  Chin-Shan Hou ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L21/28 ,  H01L49/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/28123 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/78

Abstract: A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.

Abstract translation: 所述方法包括提供半导体衬底。 第一栅极结构形成在半导体衬底上，并且邻近第一栅极结构形成牺牲栅极结构。 牺牲栅极结构可以用于使用替代栅极方法形成金属栅极结构。 覆盖第一栅极结构和牺牲栅极结构的介电层形成。 电介质层在第一栅极结构的顶表面上方具有第一厚度，并且在牺牲栅极结构的顶表面上方具有小于第一厚度的第二厚度。 （参见例如图5,15,26）。 因此，电介质层的随后的平坦化处理可能不接触第一栅极结构。

公开(公告)号：US08609495B2

公开(公告)日：2013-12-17

申请号：US12756662

申请日：2010-04-08

Applicant: Tian-Choy Gan ,  Hsien-Chin Lin ,  Chia-Pin Lin ,  Shyue-Shyh Lin ,  Li-Shiun Chen ,  Shin Hsien Liao

Inventor： Tian-Choy Gan ,  Hsien-Chin Lin ,  Chia-Pin Lin ,  Shyue-Shyh Lin ,  Li-Shiun Chen ,  Shin Hsien Liao

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/8238 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

Abstract translation: 提供一种制造半导体器件的方法，该半导体器件包括在衬底的第一和第二区域上形成第一和第二鳍片，在第一和第二鳍片上形成第一和第二栅极结构，第一和第二栅极结构包括第一和第二多晶硅栅极 ，在所述衬底上形成层间电介质（ILD），在所述ILD上进行化学机械抛光以暴露所述第一和第二多晶硅栅极，形成掩模以保护所述第一栅极结构的所述第一多晶硅栅极， 从而形成第一沟槽，去除掩模，部分地移除第一多晶硅栅极，从而形成第二沟槽，形成部分填充第一和第二沟槽的功函数金属层，形成填充第一和第二沟槽的剩余部分的填充金属层 沟槽，并且去除第一和第二沟槽外的金属层。

公开(公告)号：US06235600B1

公开(公告)日：2001-05-22

申请号：US09531403

申请日：2000-03-20

Applicant: Mu-Chi Chiang ,  Hsien-Chin Lin ,  Jiaw-Ren Shih

Inventor： Mu-Chi Chiang ,  Hsien-Chin Lin ,  Jiaw-Ren Shih

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/6656

Abstract: A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.

Abstract translation: 已经开发了用于制造用于减少热载流子电子（HEC）注入的具有离子注入氮区域的输入/输出N沟道（I / O NMOS）器件的工艺。 该过程的特征是在覆盖的氧化硅层的界面和下面的轻掺杂源极/漏极（LDD）区域上注入nitorgen区域。 在两种情况下，在氧化硅衬垫层的沉积之前或之后，可以进行注入工艺，导致在氧化物 - LDD界面处产生所需的氮堆积，以及在较梯度的LDD 个人资料 当与没有氮气注入程序制造的对手相比时，实现了对于这些I / O NMOS器件，关于HCE注入的失败时间的增加。