公开(公告)号：US20210408287A1

公开(公告)日：2021-12-30

申请号：US17348267

申请日：2021-06-15

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Van der Plas

IPC: H01L29/78 ,  H01L27/092 ,  H01L23/48 ,  H01L21/8238

Abstract: Example embodiments relate to methods for inducing stress in semiconductor devices. One method includes a method for producing a first semiconductor device and a second semiconductor device configured to conduct current through the controlled density of charge carriers in a channel area. The charge carriers of the first semiconductor device have opposite polarity to the charge carriers of the second semiconductor device. The method includes producing a stress relaxed buffer (SRD) layer. The back side of the SRB layer is positioned on a substrate. The method also includes producing a semiconductor layer on the front side of the SRB layer. Additionally, the method includes producing the first semiconductor device and the second semiconductor device on the semiconductor layer, removing the substrate, thinning the SRB layer, producing a cavity in the SRB layer, and filling the cavity with a material to create a stress compensation area.

公开(公告)号：US11121086B2

公开(公告)日：2021-09-14

申请号：US16716262

申请日：2019-12-16

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van der Plas

IPC: H01L29/78 ,  H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L23/48 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H02M3/158

Abstract: A vertical isolated gate FET transistor integrated in the front end of line of a semiconductor chip is disclosed. In one aspect, the transistor includes a modified version of a buried power rail and back side TSV (through semiconductor via) connection for connecting the front end of line to a back side signal delivery network, such as a power delivery network (PDN), the PDN being arranged on the backside of the semiconductor substrate that carries the active devices of the FEOL on its front side. In contrast to standard power rail/TSV combinations, the TSV is not electrically connected to the rail, but isolated therefrom by a dielectric plug at the bottom of the rail. The TSV is isolated from the semiconductor substrate by a dielectric liner. Well regions are furthermore provided on the front side, enveloping the rail and the dielectric plug, and on the backside, surrounding the TSV and liner. On the back side, the well includes a contact area adjacent the TSV. The TSV thereby acts as the gate of the transistor, while the rail and the contact area respectively act as source and drain or vice versa.

公开(公告)号：US11114337B2

公开(公告)日：2021-09-07

申请号：US16716025

申请日：2019-12-16

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Julien Jussot ,  Geert Van der Plas

IPC: H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A method is provided for bonding and interconnecting two semiconductor chips arranged on semiconductor substrates. HSQ (Hydrogen Silsesquioxane) or an equivalent material is used as a bonding layer and after bonding and thinning one of the wafers (or first thinning and then bonding), the bond layer is locally irradiated by an e-beam through the thinned substrate, thereby locally transforming the bonding material into silicon oxide. Then a via opening is etched through the thinned substrate and an etch process selectively removes the oxide from an area delimited by the bonding material or vice versa. The filling of the via opening establishes an electrical connection between the bonded wafers, that is equivalent to a connection obtained by hybrid bonding, but that does not suffer from the disadvantages thereof.

公开(公告)号：US20200006142A1

公开(公告)日：2020-01-02

申请号：US16456833

申请日：2019-06-28

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Stefaan Van Huylenbroeck ,  Geert Van der Plas

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/092 ,  H01L23/00

Abstract: A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

公开(公告)号：US10382042B2

公开(公告)日：2019-08-13

申请号：US16203402

申请日：2018-11-28

Applicant: IMEC vzw

Inventor： Roeland Vandebriel ,  Geert Van der Plas ,  Vladimir Cherman

IPC: H03K21/02 ,  G11C5/04 ,  G11C7/20 ,  H03K5/153 ,  H01L25/065

Abstract: An assembly including a carrier substrate and at least one group of interconnected integrated circuit modules mounted thereon is disclosed. The modules are provided with a connection for transmitting a clock signal through the group of interconnected modules. The modules are also provided with digital input ports and output ports and a logic circuit configured for identifying the position of the modules in the group on the basis of a count of the clock pulses, and on the basis of the logic state of the input and output ports. In one aspect, a method involves the transfer of a token in the form of one or more logic states, through the group of modules, from a first module to a last module, resulting in the identification of all modules in a progressive manner.

公开(公告)号：US09217861B2

公开(公告)日：2015-12-22

申请号：US14373071

申请日：2013-01-18

Applicant: IMEC VZW

Inventor： Murali Jayapala ,  Geert Van der Plas ,  Veronique Rochus ,  Xavier Rottenberg ,  Simone Severi

IPC: G02B26/00 ,  G02B27/10 ,  G02B5/08 ,  G02B26/08 ,  G02B17/08 ,  H04N13/04 ,  G02B7/182

CPC classification number: G02B26/0833 ,  G02B5/08 ,  G02B7/182 ,  G02B17/0896 ,  G02B26/08 ,  G02B26/0825 ,  G02B26/0841 ,  G02B27/10 ,  H04N13/322 ,  H04N13/365

Abstract: Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror elements arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt angle range, and each micro-mirror element in the second section has a second tilt angle range, with the first tilt angle range being less than the second tilt angle range.

Abstract translation: 这里描述了配置用于可变焦距透镜的微镜阵列。 示例性可变焦距透镜包括具有布置在至少第一部分和第二部分中的多个微反射镜元件的微反射镜阵列。 每个微镜元件具有倾斜轴线，并且在倾斜轴线的两个相对侧的每一侧上包括（i）至少一个致动电极，（ii）至少一个测量电极，和（iii）至少一个止动器。 此外，第一部分中的每个微镜元件具有第一倾斜角范围，并且第二部分中的每个微镜元件具有第二倾斜角范围，其中第一倾斜角度范围小于第二倾斜角范围。

公开(公告)号：US20140368920A1

公开(公告)日：2014-12-18

申请号：US14373071

申请日：2013-01-18

Applicant: IMEC VZW

Inventor： Murali Jayapala ,  Geert Van der Plas ,  Veronique Rochus ,  Xavier Rottenberg ,  Simone Severi

IPC: G02B26/08

CPC classification number: G02B26/0833 ,  G02B5/08 ,  G02B7/182 ,  G02B17/0896 ,  G02B26/08 ,  G02B26/0825 ,  G02B26/0841 ,  G02B27/10 ,  H04N13/322 ,  H04N13/365

Abstract: Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror element arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt axis range, and each micro-mirror element in the second section has a second tilt axis range, with the first tilt axis range being less than the second tilt axis range.

Abstract translation: 这里描述了配置用于可变焦距透镜的微镜阵列。 示例性可变焦距透镜包括具有布置在至少第一部分和第二部分中的多个微反射镜元件的微反射镜阵列。 每个微镜元件具有倾斜轴线，并且在倾斜轴线的两个相对侧的每一侧上包括（i）至少一个致动电极，（ii）至少一个测量电极，和（iii）至少一个止动器。 此外，第一部分中的每个微镜元件具有第一倾斜轴范围，并且第二部分中的每个微镜元件具有第二倾斜轴范围，其中第一倾斜轴范围小于第二倾斜轴范围。

公开(公告)号：US11822475B2

公开(公告)日：2023-11-21

申请号：US17565594

申请日：2021-12-30

Applicant: IMEC VZW

Inventor： Manu Komalan Perumkunnil ,  Geert Van der Plas

IPC: G06F12/0815 ,  G06F12/1027 ,  G06F12/0875

CPC classification number: G06F12/0815 ,  G06F12/0875 ,  G06F12/1027

Abstract: Example embodiments relate to integrated circuits with 3D partitioning. One embodiment includes an integrated circuit. The integrated circuit includes a first integrated circuit layer that includes processing cores. The integrated circuit also includes a second integrated circuit layer that includes memory arrays associated with processing cores. Additionally, the integrated circuit includes an intermediate integrated circuit layer interconnected with the first and second integrated circuit layers and including memory control logic and interface circuitries for managing data exchange between the processing cores and the memory arrays.

公开(公告)号：US11757039B2

公开(公告)日：2023-09-12

申请号：US17348267

申请日：2021-06-15

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Van der Plas

IPC: H01L29/78 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/092

CPC classification number: H01L29/7849 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/481 ,  H01L27/0924

Abstract: Example embodiments relate to methods for inducing stress in semiconductor devices. One method includes a method for producing a first semiconductor device and a second semiconductor device configured to conduct current through the controlled density of charge carriers in a channel area. The charge carriers of the first semiconductor device have opposite polarity to the charge carriers of the second semiconductor device. The method includes producing a stress relaxed buffer (SRD) layer. The back side of the SRB layer is positioned on a substrate. The method also includes producing a semiconductor layer on the front side of the SRB layer. Additionally, the method includes producing the first semiconductor device and the second semiconductor device on the semiconductor layer, removing the substrate, thinning the SRB layer, producing a cavity in the SRB layer, and filling the cavity with a material to create a stress compensation area.

公开(公告)号：US20210143211A1

公开(公告)日：2021-05-13

申请号：US17092130

申请日：2020-11-06

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Shamin Houshmand Sharifi ,  Geert Van der Plas

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/12 ,  G11C5/06

Abstract: The disclosed technology relates to the field of memory devices including memory arrays, and more particularly, to magnetic memory devices. In one aspect, the disclosed technology provides a method of fabricating a memory device, and the memory device. The method comprises: processing a plurality of selector devices in a semiconductor layer of a first substrate, processing an interconnect layer on a front-side of the semiconductor layer, the interconnect layer comprising an interconnect structure electrically connected to the plurality of selector devices, processing a plurality of memory elements in an oxide layer of the first substrate arranged on a back-side of the semiconductor layer, each memory element being electrically connected to one of the selector devices, and processing one or more vias through the semiconductor layer to electrically connect the memory elements to the interconnect structure.