公开(公告)号：US09455275B2

公开(公告)日：2016-09-27

申请号：US14168978

申请日：2014-01-30

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Maryam Shojaei Baghini ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC: H01L27/12 ,  H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L27/1211 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/78624

Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Abstract translation: 在一个实施例中，半导体器件包括设置在衬底中的第一掺杂类型的第一源。 第一掺杂型的第一漏极设置在衬底中。 第一栅极区域设置在第一源极和第一漏极之间。 第一掺杂类型的第一沟道区域设置在第一栅极区域的下方。 第二掺杂类型与第一掺杂类型相反。 第一掺杂类型的第一延伸区域设置在第一栅极和第一漏极之间。 第一延伸区域是设置在基板中或上方的第一鳍片的一部分。 第一隔离区域设置在第一延伸区域和第一漏极之间。 第一掺杂类型的第一阱区设置在第一隔离区下。 第一阱区域将第一延伸区域与第一漏极电耦合。

公开(公告)号：US20150340442A1

公开(公告)日：2015-11-26

申请号：US14743796

申请日：2015-06-18

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L29/267 ,  H01L29/45 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/1095 ,  H01L21/26513 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Abstract translation: 在本发明的实施例中，半导体器件包括具有第一掺杂类型的第一区域，具有设置在第一区域中的第一掺杂类型的沟道区域和具有第二掺杂类型的逆行阱。 第二掺杂类型与第一掺杂类型相反。 逆行井具有具有第一峰掺杂的较浅层和比第一峰掺杂高的第二峰掺杂的较深层。 该装置还包括在逆行井上具有第二掺杂型的漏极区。 延伸的漏极区域设置在逆行阱中，并且将沟道区域与漏极区域耦合。 隔离区域设置在延伸漏极区域的栅极重叠区域和漏极区域之间。 漏区的长度大于隔离区的深度。

公开(公告)号：US20140145265A1

公开(公告)日：2014-05-29

申请号：US14168978

申请日：2014-01-30

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Maryam Shojaei Baghini ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC: H01L27/12

CPC classification number: H01L27/1211 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/78624

Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Abstract translation: 在一个实施例中，半导体器件包括设置在衬底中的第一掺杂类型的第一源。 第一掺杂型的第一漏极设置在衬底中。 第一栅极区域设置在第一源极和第一漏极之间。 第一掺杂类型的第一沟道区域设置在第一栅极区域的下方。 第二掺杂类型与第一掺杂类型相反。 第一掺杂类型的第一延伸区域设置在第一栅极和第一漏极之间。 第一延伸区域是设置在基板中或上方的第一鳍片的一部分。 第一隔离区域设置在第一延伸区域和第一漏极之间。 第一掺杂类型的第一阱区设置在第一隔离区下。 第一阱区域将第一延伸区域与第一漏极电耦合。

公开(公告)号：US20140015010A1

公开(公告)日：2014-01-16

申请号：US14028403

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC: H01L29/78

CPC classification number: H01L29/1095 ,  H01L21/26513 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Abstract translation: 在本发明的实施例中，半导体器件包括具有第一掺杂类型的第一区域，具有设置在第一区域中的第一掺杂类型的沟道区域和具有第二掺杂类型的逆行阱。 第二掺杂类型与第一掺杂类型相反。 逆行井具有具有第一峰掺杂的较浅层和比第一峰掺杂高的第二峰掺杂的较深层。 该装置还包括在逆行井上具有第二掺杂型的漏极区。 延伸的漏极区域设置在逆行阱中，并且将沟道区域与漏极区域耦合。 隔离区域设置在延伸漏极区域的栅极重叠区域和漏极区域之间。 漏区的长度大于隔离区的深度。

公开(公告)号：US09647069B2

公开(公告)日：2017-05-09

申请号：US14743796

申请日：2015-06-18

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/45 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/417

CPC classification number: H01L29/1095 ,  H01L21/26513 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

公开(公告)号：US09401352B2

公开(公告)日：2016-07-26

申请号：US14712701

申请日：2015-05-14

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

IPC: H01L21/762 ,  H01L27/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0266 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region.

公开(公告)号：US20150255450A1

公开(公告)日：2015-09-10

申请号：US14712701

申请日：2015-05-14

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

IPC: H01L27/02 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0266 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region.

Abstract translation: 实施例涉及一种场效应器件，其包括主体区域，第一导电类型的第一源极/漏极区域，第二源极/漏极区域和与第一源极/漏极区域相邻的凹穴注入区域，腔体注入 区域是第二导电类型，其中第二导电类型不同于第一导电类型。 身体区域物理地接触口袋植入区域。

公开(公告)号：US09035375B2

公开(公告)日：2015-05-19

申请号：US13740048

申请日：2013-01-11

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region.

Abstract translation: 实施例涉及一种场效应器件，其包括主体区域，第一导电类型的第一源极/漏极区域，第二源极/漏极区域和与第一源极/漏极区域相邻的凹穴注入区域，腔体注入 区域是第二导电类型，其中第二导电类型不同于第一导电类型。 身体区域物理地接触口袋植入区域。

公开(公告)号：US08878234B2

公开(公告)日：2014-11-04

申请号：US13781786

申请日：2013-03-01

Applicant: Infineon Technologies AG

Inventor： Harald Gossner ,  Ramgopal Rao ,  Angada Sachid ,  Ashish Pal ,  Ram Asra

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/739 ,  H01L29/165 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L29/165 ,  H01L21/26586 ,  H01L29/0657 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/66356 ,  H01L29/7391

Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction.

Abstract translation: 在一个实施例中，提供了半导体器件。 半导体器件可以包括具有主处理表面的衬底，包括第一导电类型的第一材料的第一源极/漏极区域，包括第二导电类型的第二材料的第二源极/漏极区域，其中第二导电类型 不同于第一导电类型，电耦合在第一源极/漏极区域和第二源极/漏极区域之间的主体区域，其中主体区域在第一方向上比第一源极/漏极区域更深地延伸到衬底中 垂直于衬底的主处理表面，设置在主体区域上的栅极电介质和设置在栅极电介质上的栅极区域，其中栅极区域与第一源极/漏极区域的至少一部分重叠， 的身体区域在第一个方向。

公开(公告)号：US08686510B2

公开(公告)日：2014-04-01

申请号：US13891221

申请日：2013-05-10

Applicant: Infineon Technologies AG

Inventor： Harald Gossner ,  Christian Russ

IPC: H01L29/78

CPC classification number: H01L23/60 ,  H01L27/0262 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection element may include: a fin structure including a first connection region having a first conductivity type, a second connection region having a second conductivity type, first and second body regions formed between the connection regions, the first body region having the second conductivity type and formed adjacent to the first connection region, the second body region having the first conductivity type and formed adjacent to the second connection region, the body regions having a lower dopant concentration than the connection regions, a diffusion region formed between the body regions and having substantially the same dopant concentration as at least one of the first and second connection regions; a gate region on or above the first body region or the second body region; a gate control device electrically coupled to the gate region and configured to control at least one electrical potential applied to the gate region.

Abstract translation: ESD保护元件可以包括：翅片结构，其包括具有第一导电类型的第一连接区域，具有第二导电类型的第二连接区域，形成在连接区域之间的第一和第二主体区域，具有第二导电性的第一体区域 并且与第一连接区域相邻地形成，第二主体区域具有第一导电类型并且与第二连接区域相邻地形成，具有比连接区域低的掺杂剂浓度的体区域，形成在体区域之间的扩散区域和 具有与所述第一和第二连接区域中的至少一个基本上相同的掺杂剂浓度; 第一体区域或第二体区域上方的栅极区域; 门控制装置，其电耦合到栅极区域并且被配置为控制施加到栅极区域的至少一个电势。