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公开(公告)号：US20160301549A1
公开(公告)日：2016-10-13
申请号：US14949662
申请日：2015-11-23
Applicant: INPHI CORPORATION
Inventor： Parmanand MISHRA , Michael S. HARWOOD
IPC: H04L25/03 , H04B10/61 , H04B10/58 , H03K17/687
CPC classification number: H04L25/03885 , H03K17/687 , H04B10/58 , H04B10/6163 , H04L25/03019
Abstract: The present invention is directed to data communication systems and methods. In various embodiments, the present invention provides a CML device that changes output frequency response by varying resistance values of its load resistance and source resistance. A bias control voltage is used to adjust the tail current of the CML device, and the tail current adjusts the output gain of the CML device. There are other embodiments as well.
Abstract translation: 本发明涉及数据通信系统和方法。 在各种实施例中，本发明提供一种通过改变其负载电阻和源电阻的电阻值来改变输出频率响应的CML器件。 使用偏置控制电压来调整CML器件的尾部电流，尾电流调节CML器件的输出增益。 还有其它实施例。
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公开(公告)号：US20220103149A1
公开(公告)日：2022-03-31
申请号：US17037110
申请日：2020-09-29
Applicant: INPHI CORPORATION
Inventor： Yida DUAN , Karthik RAVIPRAKASH , Parmanand MISHRA
Abstract: The present invention is directed to communication systems and electrical circuits. According to an embodiment, the present invention provides a termination circuit that includes an inductor network. The inductor network is coupled to a termination resistor and a capacitor network, which includes a first capacitor and a second capacitor. The termination resistor, the first capacitor, and the second capacitor are adjustable, and they affect attenuation of the termination circuit. There are other embodiments as well.
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公开(公告)号：US20200059348A1
公开(公告)日：2020-02-20
申请号：US16664666
申请日：2019-10-25
Applicant: INPHI CORPORATION
Inventor： Simon FOREY , Parmanand MISHRA , Michael S. HARWOOD , Rajasekhar NAGULAPALLI
Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.
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公开(公告)号：US20170063520A1
公开(公告)日：2017-03-02
申请号：US15337072
申请日：2016-10-28
Applicant: INPHI CORPORATION
Inventor： Parmanand MISHRA , Simon FOREY
IPC: H04L7/033 , H04L27/01 , H04B17/318 , H04L12/26
CPC classification number: H04L7/0331 , H03L7/00 , H03M9/00 , H04B17/318 , H04L7/0083 , H04L7/0091 , H04L7/033 , H04L25/0262 , H04L27/01 , H04L43/04 , H04L43/16
Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides a technique for detecting loss of signal. An incoming data stream is sampled and a recovered clock signal is generated accordingly. An output clock signal of a higher frequency than the recovered clock signal is generated by a transmission PLL. The frequency of the recovered clock signal is compared to a divided frequency of the output clock signal. If a difference between the recovered clock signal and the output clock signal is greater than a threshold, a loss of signal indication is provided. There are other embodiments as well.
Abstract translation: 本发明涉及数据通信。 更具体地，本发明的实施例提供了一种用于检测信号损失的技术。 对输入数据流进行采样，并相应地生成恢复的时钟信号。 通过传输PLL产生比恢复的时钟信号高的频率的输出时钟信号。 将恢复的时钟信号的频率与输出时钟信号的分频进行比较。 如果恢复的时钟信号和输出时钟信号之间的差异大于阈值，则提供信号指示的丢失。 还有其它实施例。
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公开(公告)号：US20160330015A1
公开(公告)日：2016-11-10
申请号：US15214212
申请日：2016-07-19
Applicant: INPHI CORPORATION
Inventor： Simon FOREY , Parmanand MISHRA , Sean BATTY
IPC: H04L7/00 , H04L27/152
CPC classification number: H04L7/0087 , H03M9/00 , H04B10/6164 , H04L7/0004 , H04L7/0331 , H04L7/06 , H04L27/152
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a method for acquiring sampling frequency by sweeping through a predetermined frequency range, performing data sampling at different frequencies within the predetermined frequency range, and determining a target frequency for sampling data based on a maximum early peak frequency and a maximum late peak frequency. There are other embodiments as well.
Abstract translation: 本发明涉及数据通信。 更具体地，本发明的实施例提供一种通过扫过预定频率范围来获取采样频率的方法，在预定频率范围内以不同频率执行数据采样，并且基于最大早峰频率来确定用于采样数据的目标频率 和最大晚峰频率。 还有其它实施例。
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Patent Agency Ranking
16.发明申请SERIALIZER/DESERIALIZER APPARATUS WITH LOOPBACK CONFIGURATION AND METHODS THEREOF 有权具有回放配置的SERIALIZER / DESERIALIZER设备及其方法公开(公告)号：US20150016493A1
公开(公告)日：2015-01-15
申请号：US14479121
申请日：2014-09-05
Applicant: INPHI CORPORATION
Inventor： Parmanand MISHRA , Michael S. HARWOOD
CPC classification number: H04L25/063 , H03M9/00 , H04B1/38 , H04B3/04 , H04B3/14
Abstract: The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer are directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.
Abstract translation: 本发明涉及集成电路。 在具体实施例中，来自均衡器的高频信号直接连接到读出放大器的第一对输入端。 读出放大器还具有第二对输入，其可以选择性地耦合到来自DAC或高频环回信号的输出信号。 还有其它实施例。
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公开(公告)号：US20190207788A1
公开(公告)日：2019-07-04
申请号：US16295210
申请日：2019-03-07
Applicant: INPHI CORPORATION
Inventor： Richard WARD , Parmanand MISHRA
CPC classification number: H04L25/03885 , H03M9/00 , H04L7/0016 , H04L7/02 , H04L25/03012 , H04L27/22
Abstract: The present invention is directed to data communication. In a specific embodiment, a known data segment is received through a data communication link. The received data is equalized by an equalizer using an adjustable equalization parameter. The output of the equalizer is sampled, and a waveform is obtained by sweeping one or more sampler parameters. The waveform is evaluated by comparing it to the known data segment. Based on the quality of the waveform, equalizer parameter is determined. There are other embodiments as well.
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公开(公告)号：US20190044521A1
公开(公告)日：2019-02-07
申请号：US16154522
申请日：2018-10-08
Applicant: INPHI CORPORATION
Inventor： Simon FOREY , Rajasekhar NAGULAPALLI , Parmanand MISHRA
CPC classification number: H03L7/0807 , H03G3/20 , H03K5/1565 , H04L27/01
Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.
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公开(公告)号：US20180294899A1
公开(公告)日：2018-10-11
申请号：US15995042
申请日：2018-05-31
Applicant: INPHI CORPORATION
Inventor： Simon FOREY , Rajasekhar NAGULAPALLI , Parmanand MISHRA , Michael S. HARWOOD
IPC: H04B17/21 , H04B17/318 , H04L12/26 , H03K5/19 , H03K3/3565
CPC classification number: H04B17/21 , H03K3/3565 , H03K5/19 , H04B17/318
Abstract: The present invention is directed to data communication. According to a specific embodiment, the present invention provides technique for loss of signal detection. A loss-of-signal detection (LOSD) device determines an analog signal indicating signal strength by subtracting a threshold offset voltage from an incoming signal. The analog signal is then processed by a switch network of an output stage circuit, which provides a digital output of loss of signal indication at a low frequency (relative to the incoming signal frequency). There are other embodiments as well.
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公开(公告)号：US20180183444A1
公开(公告)日：2018-06-28
申请号：US15840984
申请日：2017-12-13
Applicant: INPHI CORPORATION
Inventor： Simon FOREY , Rajasekhar NAGULAPALLI , Parmanand MISHRA
CPC classification number: H03L7/0807 , H03G3/20 , H03K5/1565 , H04L27/01
Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.
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