公开(公告)号：US09472248B2

公开(公告)日：2016-10-18

申请号：US14228856

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Zeshan A. Chishti ,  Jaewoong Sim

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F12/122 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0673 ,  G06F12/0893 ,  G06F2212/1016 ,  G11C7/1072

Abstract: An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.

Abstract translation: 描述了用于实现异构存储器子系统的装置和方法。 例如，处理器的一个实施例包括：存储器映射逻辑，用于将系统存储器空间细分成多个存储器块，并且跨越第一存储器和第二存储器映射存储器块，第一存储器具有第一组存储器访问 特性和第二存储器具有不同于第一组存储器访问特性的第二组存储器存取特性; 以及动态重映射逻辑，用于至少部分地基于访问存储器块的检测频率来交换第一和第二存储器之间的存储器块。

公开(公告)号：US09223710B2

公开(公告)日：2015-12-29

申请号：US13844823

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： Alaa R. Alameldeen ,  Christopher B. Wilkerson ,  Samira M. Khan

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0864 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/127 ,  G06F2212/604

Abstract: A system and method to enforce read-write partitioning in an N-way, set associative cache may limit a number of ways allocated for storing modified data in a set to a value W and limit a number of ways holding read data to a value R. The cache may be configured where N=R+W. Furthermore, a number of ways storing prefetched read data may be limited to RP, while a number of ways storing prefetched modified data may be limited to WP. The values for W, R, WP, and/or RP may be determined using a prediction method to estimate cache miss rates for different values for W, R, WP, and/or RP and selecting values corresponding to a desired cache miss rate, and so allowing for selective application of the read-write partitioning.

Abstract translation: 在N路设置关联高速缓存中强制执行读写分区的系统和方法可能限制分配用于将集合中的修改数据存储为值W的方式的数量，并限制将读取数据保存为值R的多种方式 可以配置高速缓存，其中N = R + W。 此外，存储预取的读取数据的多种方式可以限于RP，而存储预取修改数据的多种方式可能被限制为WP。 可以使用预测方法来确定W，R，WP和/或RP的值，以估计用于W，R，WP和/或RP的不同值的高速缓存未命中率，并且选择对应于期望的高速缓存未命中率的值， 因此允许选择性地应用读写分区。

公开(公告)号：US20140281248A1

公开(公告)日：2014-09-18

申请号：US13844823

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： Alaa R. Alameldeen ,  Christopher B. Wilkerson ,  Samira M. Khan

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/127 ,  G06F2212/604

Abstract: A system and method to enforce read-write partitioning in an N-way, set associative cache may limit a number of ways allocated for storing modified data in a set to a value W and limit a number of ways holding read data to a value R. The cache may be configured where N=R+W. Furthermore, a number of ways storing prefetched read data may be limited to RP, while a number of ways storing prefetched modified data may be limited to WP. The values for W, R, WP, and/or RP may be determined using a prediction method to estimate cache miss rates for different values for W, R, WP, and/or RP and selecting values corresponding to a desired cache miss rate, and so allowing for selective application of the read-write partitioning.

Abstract translation: 在N路设置关联高速缓存中强制执行读写分区的系统和方法可能限制分配用于将集合中的修改数据存储为值W的方式的数量，并限制将读取数据保存为值R的多种方式 可以配置高速缓存，其中N = R + W。 此外，存储预取的读取数据的多种方式可以限于RP，而存储预取修改数据的多种方式可能被限制为WP。 可以使用预测方法来确定W，R，WP和/或RP的值，以估计用于W，R，WP和/或RP的不同值的高速缓存未命中率，并且选择对应于期望的高速缓存未命中率的值， 因此允许选择性地应用读写分区。

公开(公告)号：US11853758B2

公开(公告)日：2023-12-26

申请号：US16585521

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Berkin Akin ,  Alaa R. Alameldeen

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30087

Abstract: Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.

公开(公告)号：US11544093B2

公开(公告)日：2023-01-03

申请号：US16586859

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Andrew V. Anderson ,  Alaa R. Alameldeen ,  Andrew M. Rudoff

IPC: G06F9/455

Abstract: Examples herein relate to checkpoint replication and copying of updated checkpoint data. For example, a memory controller coupled to a memory can receive a write request with an associated address to write or update checkpoint data and track updates to checkpoint data based on at least two levels of memory region sizes. A first level is associated with a larger memory region size than a memory region size associated with the second level. In some examples, the first level is a cache-line memory region size and the second level is a page memory region size. Updates to the checkpoint data can be tracked at the second level unless an update was previously tracked at the first level. Reduced amounts of updated checkpoint data can be transmitted during a checkpoint replication by using multiple region size trackers.

公开(公告)号：US11074188B2

公开(公告)日：2021-07-27

申请号：US16278509

申请日：2019-02-18

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Lidia Warnes ,  Andy M. Rudoff ,  Muthukumar P. Swaminathan

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/02 ,  G06F12/0893

Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

公开(公告)号：US20200026655A1

公开(公告)日：2020-01-23

申请号：US16586251

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Alaa R. Alameldeen ,  Yi Zou ,  Gordon King

IPC: G06F12/0873 ,  G06F12/0811 ,  G06F12/0897 ,  G06F12/02 ,  G06F13/16

Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

公开(公告)号：US10261901B2

公开(公告)日：2019-04-16

申请号：US14865617

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Zhe Wang ,  Christopher B. Wilkerson ,  Zeshan A. Chishti ,  Seth H. Pugsley ,  Alaa R. Alameldeen ,  Shih-Lien L. Lu

IPC: G06F12/00 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/0893 ,  G06F13/00 ,  G06F13/28

Abstract: An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.

公开(公告)号：US20190042422A1

公开(公告)日：2019-02-07

申请号：US15927715

申请日：2018-03-21

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Alaa R. Alameldeen

IPC: G06F12/0811 ,  G06F12/0804

Abstract: One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores cache blocks that at least partially include a subset of cache blocks stored by near memory circuitry. The near memory circuitry is configured in an n-way set associative format that references the cache blocks stored by the near memory circuitry using set identifiers and way identifiers. The cache management circuitry stores way identifiers for the cache blocks of the near memory circuitry within the cache blocks in the last level cache circuitry. Storing way identifiers in the cache blocks of the last level cache enables the cache management circuitry or memory controller circuitry to write back a cache block without reading tags in one or more ways of the near memory circuitry.

公开(公告)号：US20180173636A1

公开(公告)日：2018-06-21

申请号：US15385604

申请日：2016-12-20

Applicant: Intel Corporation

Inventor： Elizabeth Reed ,  Alaa R. Alameldeen ,  Helia Naeimi ,  Patrick F. Stolt

IPC: G06F12/0891

CPC classification number: G06F12/0891 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1036 ,  G06F2212/60

Abstract: A first request to evict a first cache line that is stored in a cache memory may be received. The first cache line may be evicted based on a replacement policy. A second request to evict a second cache line from the cache memory may be received. Following the receipt of the second request, it is determined whether a condition associated with the replacement policy has been satisfied. If the condition associated with replacement policy has been satisfied, then the second cache line may be evicted based on a random replacement policy.