公开(公告)号：US20230099517A1

公开(公告)日：2023-03-30

申请号：US17561452

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Asit Mallick ,  Rajesh Sankaran ,  Hisham Shafi ,  Vedvyas Shanbhogue ,  Vivekananthan Sanjeepan ,  Jason Brandt

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/30

Abstract: Processors, methods, and systems for user-level interprocessor interrupts are described. In an embodiment, a processing system includes a memory and a processing core. The memory is to store an interrupt control data structure associated with a first application being executed by the processing system. The processing core includes an instruction decoder to decode a first instruction, invoked by a second application, to send an interprocessor interrupt to the first application; and, in response to the decoded instruction, is to determine that an identifier of the interprocessor interrupt matches a notification interrupt vector associated with the first application; set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interprocessor interrupt; and invoke an interrupt handler for the interprocessor interrupt identified by the interrupt control data structure.

公开(公告)号：US20220207154A1

公开(公告)日：2022-06-30

申请号：US17134333

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Richard Winterton ,  Mohammad Reza Haghighat ,  Asit Mallick ,  Alaa Alameldeen ,  Abhishek Basak ,  Jason W. Brandt ,  Michael Chynoweth ,  Carlos Rozas ,  Scott Constable ,  Martin Dixon ,  Matthew Fernandez ,  Fangfei Liu ,  Francis McKeen ,  Joseph Nuzman ,  Gilles Pokam ,  Thomas Unterluggauer ,  Xiang Zou

IPC: G06F21/60 ,  H04L9/08 ,  H04L9/30

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.

公开(公告)号：US20220207148A1

公开(公告)日：2022-06-30

申请号：US17134345

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC: G06F21/57 ,  G06F9/38 ,  G06F21/54

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and branch circuitry coupled to the decode circuitry. The decode circuitry is to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack. The branch circuitry is to be hardened in response to the branch hardening instruction.

公开(公告)号：US20220207146A1

公开(公告)日：2022-06-30

申请号：US17134341

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC: G06F21/57 ,  G06F9/38 ,  G06F21/54

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and load circuitry coupled to the decode circuitry. The decode circuitry is to decode a load hardening instruction to mitigate vulnerability to a speculative execution attack. The load circuitry is to be hardened in response to the load hardening instruction.

公开(公告)号：US09164764B2

公开(公告)日：2015-10-20

申请号：US14286536

申请日：2014-05-23

Applicant: INTEL CORPORATION

Inventor： Ethan Schuchman ,  Hong Wang ,  Chris Weaver ,  Belliappa M. Kuttanna ,  Asit Mallick ,  Vivek K. De ,  Per Hammarlund

IPC: G06F9/30 ,  G06F1/32 ,  G06F9/46

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3265 ,  G06F1/3268 ,  G06F1/3296 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/461 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/153 ,  Y02D10/154 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.

Abstract translation: 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。

公开(公告)号：US20220207149A1

公开(公告)日：2022-06-30

申请号：US17134347

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Joseph Nuzman ,  Asit Mallick ,  Carlos Rozas

IPC: G06F21/57 ,  G06F21/75 ,  G06F21/53

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability detection hardware and execution hardware. The speculation vulnerability detection hardware is to detect vulnerability to a speculative execution attack and, in connection with a detection of vulnerability to a speculative execution attack, to provide an indication that data from a first operation is tainted. The execution hardware is to perform a second operation using the data if the second operation is to be performed non-speculatively and to prevent performance of the second operation if the second operation is to be performed speculatively and the data is tainted.

公开(公告)号：US20220206819A1

公开(公告)日：2022-06-30

申请号：US17134335

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Gilles Pokam ,  Asit Mallick ,  Martin Dixon ,  Michael Chynoweth

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability mitigation hardware and speculation vulnerability detection hardware. The speculation vulnerability mitigation hardware is to implement one or more of a plurality of speculation vulnerability mitigation mechanisms. The speculation vulnerability detection hardware to detect vulnerability to a speculative execution attack and to provide to software an indication of speculative execution attack vulnerability.

公开(公告)号：US20220206818A1

公开(公告)日：2022-06-30

申请号：US17134334

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Alaa Alameldeen ,  Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC: G06F9/38 ,  G06F9/30 ,  G06F21/57

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a single instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the single instruction.

公开(公告)号：US09977743B2

公开(公告)日：2018-05-22

申请号：US15252719

申请日：2016-08-31

Applicant: Intel Corporation

Inventor： Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Carlos V. Rozas ,  Somnath Chakrabarti ,  Asit Mallick

IPC: G06F12/08 ,  G06F21/57 ,  G06F12/0817 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0824 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F21/53 ,  G06F21/572 ,  G06F2212/1008 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2221/032

Abstract: A processing device includes a first counter having a first count value of a number of child pages among a plurality of child pages present in an enclave memory of a first virtual machine (VM). The plurality of child pages are associated with a parent page in the enclave memory. The processing device includes a second counter having a second count value of a number of child pages among the plurality of child pages not present in the enclave memory and being shared by a second VM, wherein the second VM is different from the first VM. A non-zero value of at least one of the first counter or the second counter prevents eviction of the parent page from the enclave memory.