公开(公告)号：US20250008852A1

公开(公告)日：2025-01-02

申请号：US18346212

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dominique A. Adams ,  Gauri Auluck ,  Scott B. Clendenning ,  Arnab Sen Gupta ,  Brandon Holybee ,  Raseong Kim ,  Matthew V. Metz ,  Kevin P. O'Brien ,  John J. Plombon ,  Marko Radosavljevic ,  Carly Rogan ,  Hojoon Ryu ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  I-Cheng Tung ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov

IPC: H10N70/00 ,  H10B63/00 ,  H10B99/00

Abstract: A two-terminal ferroelectric perovskite diode comprises a region of ferroelectric perovskite material positioned adjacent to a region of n-type doped perovskite semiconductor material. Asserting a positive voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a first direction that causes the diode to be placed in a low resistance state due to the formation of an accumulation region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor boundary. Asserting a negative voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a second direction that causes the diode to be placed in a high resistance state due to the formation of a depletion region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor material. These non-volatile low and high resistance states enable the diode to be used as a non-volatile memory element.

公开(公告)号：US20240222126A1

公开(公告)日：2024-07-04

申请号：US18147644

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Uygar Avci ,  Brandon Holybee ,  Jennifer Lux ,  Kevin O'Brien ,  Shida Tan

IPC: H01L21/266 ,  H01L21/265

CPC classification number: H01L21/266 ,  H01L21/26506

Abstract: This disclosure describes systems, apparatus, methods, and devices related to fabrication using ion beams. The device may apply an ion beam targeted to at least one of one or more regions of a top layer, a metal layer placed on top of the top layer, or one or more ion stoppers placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify the material characteristics of the 2D material at the one or more regions of the top layer. The device may create a bond between the one or more 2D and metal layers to the one or more regions of the top layer where the material characteristics of the 2D material have been modified due to the impinging ion beam.

公开(公告)号：US20240222073A1

公开(公告)日：2024-07-04

申请号：US18147636

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Shida Tan ,  Uygar Avci ,  Brandon Holybee ,  Kirby Maxey ,  Kevin O'Brien ,  Mahmut Sami Kavrik

IPC: H01J37/317 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01J37/3174 ,  H01L21/0279 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139 ,  H01J2237/3174 ,  H01J2237/31755

Abstract: This disclosure describes systems, apparatus, methods, and devices related to ion beams fabrication. A device may overlay a wafer assembly of one or more layers with a top layer comprised of a material having 2D material characteristics. The device may be fabricated by applying an ion beam targeted to at least one of one or more regions of the top layer or a resist layer placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify material characteristics of the resist layer or to perform milling of the top layer or other layers of the one or more layers of the wafer assembly.

公开(公告)号：US20240120415A1

公开(公告)日：2024-04-11

申请号：US17958362

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Sudarat Lee ,  Kevin P. O'Brien ,  Rachel A. Steinhardt ,  John J. Plombon ,  Arnab Sen Gupta ,  Charles C. Mokhtarzadeh ,  Gauri Auluck ,  Tristan A. Tronic ,  Brandon Holybee ,  Matthew V. Metz ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/778 ,  H01L21/02197 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/78391

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.