公开(公告)号：US20180284879A1

公开(公告)日：2018-10-04

申请号：US15477046

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Eugene Gorbatov ,  Alexander B. Uan-Zo-Li ,  Muhammad Abozaed ,  Efraim Rotem ,  Tod F. Schiff ,  James G. Hermerding, II ,  Chee Lim Nge

IPC: G06F1/32 ,  G06F15/78

Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.

公开(公告)号：US20170139864A1

公开(公告)日：2017-05-18

申请号：US15419443

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Tod Schiff ,  Vijayakumar Dibbad ,  Alan Hallberg

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F13/382 ,  G06F13/4068 ,  G06F13/4282

Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.

公开(公告)号：US20160378633A1

公开(公告)日：2016-12-29

申请号：US14752937

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Nitin V. Sarangdhar ,  Mukesh Kataria ,  Chee Lim Nge ,  Basavaraj B. Astekar ,  Karthi R. Vadivelu

IPC: G06F11/30 ,  G06F11/263 ,  G06F13/42

CPC classification number: G06F13/4282

Abstract: A repair engine for a computing platform is separate from the repeatedly-rewritten storage components for software and firmware. For example, the repair engine may reside in ROM or hardware logic. Through dedicated connections to one or more controllers, the repair engine detects when any of the platform's dual-role ports (e.g., on-the-go USB ports) is connected to a host device. The repair engine responds by opening firmware-independent communication with the host device and supporting the downloading and execution (DnX) of a firmware image from the host. Because the communication is initiated independently of the firmware, even a catastrophic firmware failure is repairable without requiring a user to identify and use a specially modified port.

Abstract translation: 用于计算平台的修复引擎与用于软件和固件的重复重写的存储组件分开。 例如，修复引擎可以驻留在ROM或硬件逻辑中。 通过与一个或多个控制器的专用连接，修复引擎检测何时平台的任何双重角色端口（例如，移动USB端口）连接到主机设备。 修复引擎通过打开与主机设备的固件无关的通信来响应，并支持来自主机的固件映像的下载和执行（DnX）。 由于通信是独立于固件启动的，即使是灾难性的固件故障也是可修复的，无需用户识别和使用特殊修改的端口。

公开(公告)号：US20250060803A1

公开(公告)日：2025-02-20

申请号：US18474385

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Sapumal Wijeratne ,  Stephen H. Gunther ,  Rene Barrientos Barrientos ,  Joseph Alberts ,  Preeti Agarwal ,  Chee Lim Nge ,  Jorge Rodriguez

IPC: G06F1/3209

Abstract: In one example, an apparatus comprises a first intellectual property (IP) circuit to execute operations on data and a power controller. The power controller is to: receive a boost value that is based at least in part on one or more characteristics of a power supply; determine a boosted maximum power level based at least in part on the boost value and a legacy maximum power level; and provide a boosted maximum power budget for the first IP circuit based at least in part on the boosted maximum power level. The first IP circuit, in response to an input voltage violation signal, is to reactively reduce power consumption equal to or below a legacy maximum power budget for the first IP circuit lower than the boosted maximum power budget. Other embodiments are described and claimed.

公开(公告)号：US11429173B2

公开(公告)日：2022-08-30

申请号：US16230440

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Amit Jain ,  Anant Deval ,  Nimrod Angel ,  Fabrice Paillet ,  Michael Zelikson ,  Sergio Carlo Rodriguez

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  H02M3/158 ,  H02M1/08 ,  G06F1/20 ,  G06F1/3296 ,  H02M1/32 ,  G06F1/324 ,  H02M1/00 ,  H02M3/156

Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.

公开(公告)号：US20220091656A1

公开(公告)日：2022-03-24

申请号：US17030175

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Alexander Uan-Zo-li ,  Zhongsheng Wang ,  James Hermerding, II ,  Caren Magi

IPC: G06F1/3212 ,  G06F1/3234

Abstract: A driver (e.g., a firmware or software) that improves the performance of the system-on-chip (SoC) in battery mode. The driver is a Peak Power Manager (PPM) which allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. The PPM sets the Vth threshold voltage (the voltage level at which the platform will throttle the SoC) in such a way as to prevent the system from unexpected shutdown (or black screening). The PPM calculates the Psoc,pk SoC Peak Power Limit (e.g., PL4), according to the threshold voltage (Vth). These are two dependent parameters, if one is set, the other can be calculated. The scheme by the PPM is used to optimally set one parameter (Vth) based on the system parameters, and the history of the operation.

公开(公告)号：US20210318741A1

公开(公告)日：2021-10-14

申请号：US17306778

申请日：2021-05-03

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  James Hermerding II ,  Zhongsheng Wang ,  Pranava Alekal

IPC: G06F1/3203

Abstract: Described are mechanisms and methods for implementing highly configurable power delivery management policies. An apparatus may comprise a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may include a memory to store a first table having one or more first entries and to store a second table having one or more respectively corresponding second entries. The second circuitry may, upon the occurrence of an event, test a condition specified by an entry in the first table. The third circuitry may, upon the test of the condition having a positive result, evaluate a set of one or more parameters as specified by an entry in a second table corresponding with the entry in the first table. The fourth circuitry may initiate a power-management action based upon the evaluation of the set of one or more parameters.

公开(公告)号：US10431976B2

公开(公告)日：2019-10-01

申请号：US15466498

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Alexander B. Uan-Zo-li ,  Eugene Gorbatov ,  Chee Lim Nge

IPC: H02J1/00 ,  H02J7/00 ,  G01R31/3835 ,  H02J1/02 ,  H02J7/34

Abstract: A method and apparatus for extending peak power capability of a computing device. In one embodiment, the apparatus comprises: voltage monitoring hardware to monitor voltage being supplied by a battery to a system load; and an energy storage coupled to the voltage monitoring hardware and/or charging scheme to supplement supply of power to the system load when the voltage supplied to the system load by the battery, as monitored by the voltage monitoring hardware, drops below a first threshold voltage level, the first threshold voltage level being above a minimum voltage level associated with the computing system.

公开(公告)号：US10241954B2

公开(公告)日：2019-03-26

申请号：US15396527

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Chee Lim Nge ,  Basavaraj B. Astekar ,  Jenn Chuan Cheng

IPC: G06F13/20 ,  G06F13/42 ,  G06F1/26 ,  G06F1/3287

Abstract: In some examples, a power delivery system includes a primary power path to provide power to a computing system. The power delivery system also includes a bypass power path. A port manager is to disable the primary power path and to enable the bypass power path in response to a dead battery condition.

公开(公告)号：US20190041969A1

公开(公告)日：2019-02-07

申请号：US15969198

申请日：2018-05-02

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  James G. Hermerding, II ,  Pronay Dutta ,  Joshua Resch

IPC: G06F1/32 ,  G06F9/48

Abstract: In one embodiment, a processor includes: a plurality of processing elements to perform operations; a power management agent (PMA) coupled to the plurality of processing elements to control power consumption of the plurality of processing elements; and a throttling circuit coupled to the PMA. The throttling circuit is to determine a throttling power level for the plurality of processing elements based at least in part on translation information communicated from the PMA. Other embodiments are described and claimed.