公开(公告)号：US20190123164A1

公开(公告)日：2019-04-25

申请号：US16230454

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US11824002B2

公开(公告)日：2023-11-21

申请号：US16457712

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan ,  Jiansheng Xu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209

Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.

公开(公告)号：US10930729B2

公开(公告)日：2021-02-23

申请号：US16328704

申请日：2016-10-21

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Neville L. Dias ,  Rahul Ramaswamy ,  Hsu-Yu Chang ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L49/02 ,  H01L21/285 ,  H01L21/306 ,  H01L27/06 ,  C23C16/455

Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.

公开(公告)号：US10923574B2

公开(公告)日：2021-02-16

申请号：US16569879

申请日：2019-09-13

Applicant: INTEL CORPORATION

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Jui-Yen Lin ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/3213 ,  H01L21/764 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US10854757B2

公开(公告)日：2020-12-01

申请号：US16344226

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Hsu-Yu Chang ,  Chia-Hong Jan ,  Walid M. Hafez ,  Neville L. Dias ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.

公开(公告)号：US10761264B2

公开(公告)日：2020-09-01

申请号：US16462077

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Chia-Hong Jan ,  Walid Hafez ,  Neville Dias ,  Hsu-Yu Chang ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/00 ,  H01P3/16 ,  G02B6/134 ,  G02B6/136

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.

公开(公告)号：US10756210B2

公开(公告)日：2020-08-25

申请号：US16317708

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Neville L. Dias ,  Rahul Ramaswamy ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L51/05 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.

公开(公告)号：US10204999B2

公开(公告)日：2019-02-12

申请号：US15743847

申请日：2015-07-17

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L21/764 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US11063137B2

公开(公告)日：2021-07-13

申请号：US16302698

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Jui-Yen Lin ,  Chen-Guan Lee ,  Joodong Park ,  Walid M. Hafez ,  Kun-Huan Shih

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/265

Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.

公开(公告)号：US10892261B2

公开(公告)日：2021-01-12

申请号：US16318107

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Roman W. Olac-Vaw ,  Joodong Park ,  Chen-Guan Lee ,  Chia-Hong Jan

IPC: H01L27/088 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78

Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.