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    EXTENSION OF NANOCOMB TRANSISTOR ARRANGEMENTS TO IMPLEMENT GATE ALL AROUND
    17.
    发明申请
    EXTENSION OF NANOCOMB TRANSISTOR ARRANGEMENTS TO IMPLEMENT GATE ALL AROUND 有权

    公开(公告)号：US20220093474A1

    公开(公告)日：2022-03-24

    申请号：US17030449

    申请日：2020-09-24

    Applicant: Intel Corporation

    Inventor： Varun Mishra ,  Stephen M. Cea ,  Cory E. Weber ,  Jack T. Kavalieros ,  Tahir Ghani

    IPC: H01L21/84 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

    Abstract: Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

    SOURCE/DRAIN REGIONS IN INTEGRATED CIRCUIT STRUCTURES
    18.
    发明申请
    SOURCE/DRAIN REGIONS IN INTEGRATED CIRCUIT STRUCTURES 有权

    公开(公告)号：US20210384307A1

    公开(公告)日：2021-12-09

    申请号：US16891950

    申请日：2020-06-03

    Applicant: Intel Corporation

    Inventor： Sean T. Ma ,  Cory E. Weber

    IPC: H01L29/417 ,  H01L29/786 ,  H01L29/78

    Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a channel region including a semiconductor material; and a source/drain region at a side face of the channel region, wherein the source/drain region includes a semiconductor portion and a contact metal, and the semiconductor portion is between the contact metal and the semiconductor material.

    Techniques for increasing channel region tensile strain in n-MOS devices
    19.
    发明授权
    Techniques for increasing channel region tensile strain in n-MOS devices 有权

    公开(公告)号：US11011620B2

    公开(公告)日：2021-05-18

    申请号：US16322815

    申请日：2016-09-27

    Applicant: INTEL CORPORATION

    Inventor： Rishabh Mehandru ,  Cory E. Weber ,  Anand S. Murthy ,  Karthik Jambunathan ,  Glenn A. Glass ,  Jiong Zhang ,  Ritesh Jhaveri ,  Szuya S. Liao

    IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/32

    Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.

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