公开(公告)号：US11018222B1

公开(公告)日：2021-05-25

申请号：US16728088

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Daniel B. O'Brien ,  Christopher J. Wiegand ,  Lukas M. Baumgartel ,  Oleg Golonzka ,  Dan S. Lavric ,  Daniel B. Bergstrom ,  Jeffrey S. Leib ,  Timothy Michael Duffy ,  Dax M. Crum

IPC: H01L29/06 ,  H01L23/00 ,  B82B1/00

Abstract: Disclosed herein are structures, methods, and assemblies related to metallization in integrated circuit (IC) structures. For example, in some embodiments, an IC structure may include a first nanowire in a metal region and a second nanowire in the metal region. A distance between the first nanowire and the second nanowire may be less than 5 nanometers, and the metal region may include tungsten between the first nanowire and the second nanowire.

公开(公告)号：US09812546B2

公开(公告)日：2017-11-07

申请号：US15401965

申请日：2017-01-09

Applicant: Intel Corporation

Inventor： Sameer S. Pradhan ,  Daniel B. Bergstrom ,  Jin-Sung Chun ,  Julia Chiu

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  C23C14/06 ,  H01L29/417 ,  H01L23/522 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/4966 ,  C22C30/00 ,  C23C14/0635 ,  C23C14/0652 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

公开(公告)号：US09637810B2

公开(公告)日：2017-05-02

申请号：US14860336

申请日：2015-09-21

Applicant: INTEL CORPORATION

Inventor： Sameer S. Pradhan ,  Daniel B. Bergstrom ,  Jin-Sung Chun ,  Julia Chiu

IPC: H01L27/088 ,  C22C30/00 ,  H01L29/45 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/4966 ,  C22C30/00 ,  C23C14/0635 ,  C23C14/0652 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

公开(公告)号：US11063151B2

公开(公告)日：2021-07-13

申请号：US16481028

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Daniel B. Bergstrom ,  Christopher J. Wiegand

IPC: H01L23/532 ,  H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8234

Abstract: Metal chemical vapor deposition approaches for fabricating wrap-around contacts, and semiconductor structures having wrap-around metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor feature above a substrate. A dielectric layer is over the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-flat topography. A metallic contact material is directly on the portion of the semiconductor feature. The metallic contact material is conformal with the non-flat topography of the portion of the semiconductor feature. The metallic contact material has a total atomic composition including 95% or greater of a single metal species.

公开(公告)号：US20190088538A1

公开(公告)日：2019-03-21

申请号：US16081713

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Daniel J. Zierath ,  Jason A. Farmer ,  Daniel B. Bergstrom

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  C23C16/34 ,  C23C16/455

Abstract: In an example, there is disclosed a chemical compound, including a transition metal, a post-transition metal, a metalloid, and a nonmetal. By way of non-limiting example, the post-transition metal may be aluminum. The transition metal is selected from the group consisting of tungsten, tantalum, hafnium, molybdenum, niobium, zirconium, vanadium, and titanium. The metalloid may be boron or silicon. The nonmetal may be carbon or nitrogen. The compound may be used, for example, as a barrier material in an integrated circuit.

公开(公告)号：US10096513B2

公开(公告)日：2018-10-09

申请号：US15619283

申请日：2017-06-09

Applicant: Intel Corporation

Inventor： Jason A. Farmer ,  Jeffrey S. Leib ,  Daniel B. Bergstrom

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/28 ,  H01L23/532 ,  H01L23/528 ,  H01L21/285 ,  H01L29/51

Abstract: An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.

公开(公告)号：US20180047825A1

公开(公告)日：2018-02-15

申请号：US15726609

申请日：2017-10-06

Applicant: Intel Corporation

Inventor： Sameer S. Pradhan ,  Daniel B. Bergstrom ,  Jin-Sung Chun ,  Julia Chiu

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L23/522 ,  C23C14/06 ,  H01L29/78

CPC classification number: H01L29/4966 ,  C22C30/00 ,  C23C14/0635 ,  C23C14/0652 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

公开(公告)号：US09711399B2

公开(公告)日：2017-07-18

申请号：US15100531

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Jason A. Farmer ,  Jeffrey S. Leib ,  Daniel B. Bergstrom

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/28 ,  H01L23/528 ,  H01L23/532 ,  H01L29/51 ,  H01L21/285

CPC classification number: H01L21/76856 ,  H01L21/28088 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76867 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/517

Abstract: An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.