公开(公告)号：US20240088153A1

公开(公告)日：2024-03-14

申请号：US18513028

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Nicole THOMAS ,  Ehren MANNEBACH ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

公开(公告)号：US20220352032A1

公开(公告)日：2022-11-03

申请号：US17866122

申请日：2022-07-15

Applicant: INTEL CORPORATION

Inventor： Aaron D. LILAK ,  Ehren MANNEBACH ,  Anh PHAN ,  Richard E. SCHENKER ,  Stephanie A. BOJARSKI ,  Willy RACHMADY ,  Patrick R. MORROW ,  Jeffrey D. BIELEFELD ,  Gilbert DEWEY ,  Hui Jae YOO

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/48

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US20220102346A1

公开(公告)日：2022-03-31

申请号：US17547147

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Ehren MANNEBACH ,  Patrick MORROW ,  Willy RACHMADY

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/10

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

公开(公告)号：US20200211905A1

公开(公告)日：2020-07-02

申请号：US16236156

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Gilbert DEWEY ,  Aaron LILAK ,  Kimin JUN ,  Brennen MUELLER ,  Ehren MANNEBACH ,  Anh PHAN ,  Patrick MORROW ,  Hui Jae YOO ,  Jack T. KAVALIEROS

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20250107183A1

公开(公告)日：2025-03-27

申请号：US18372514

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Gilbert DEWEY ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Ehren MANNEBACH ,  Shaun MILLS ,  Charles H. WALLACE

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having differentiated source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width and a composition. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having the composition of the first epitaxial source or drain structure, and the second epitaxial source or drain structure having a lateral width less than the lateral width of the first epitaxial source or drain structure.

公开(公告)号：US20240429291A1

公开(公告)日：2024-12-26

申请号：US18214262

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Shaun MILLS ,  Ehren MANNEBACH

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having backside source or drain contact selectivity are described. In an example, an integrated circuit structure includes a first epitaxial source or drain structure at an end of a first plurality of horizontally stacked nanowires or fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at an end of a second plurality of horizontally stacked nanowires or fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact.

公开(公告)号：US20240371700A1

公开(公告)日：2024-11-07

申请号：US18774351

申请日：2024-07-16

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Ehren MANNEBACH ,  Anh PHAN ,  Richard E. SCHENKER ,  Stephanie A. BOJARSKI ,  Willy RACHMADY ,  Patrick R. MORROW ,  Jeffrey D. BIELEFELD ,  Gilbert DEWEY ,  Hui Jae YOO

IPC: H01L21/8234 ,  H01L23/48 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US20240162141A1

公开(公告)日：2024-05-16

申请号：US18419015

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Rishabh MEHANDRU

IPC: H01L23/522 ,  H01L21/8234 ,  H01L25/16 ,  H01L29/06

CPC classification number: H01L23/5226 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823481 ,  H01L25/16 ,  H01L29/0653

Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

公开(公告)号：US20230369399A1

公开(公告)日：2023-11-16

申请号：US18225440

申请日：2023-07-24

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Anh PHAN ,  Aaron LILAK ,  Willy RACHMADY ,  Gilbert DEWEY ,  Cheng-Ying HUANG ,  Richard SCHENKER ,  Hui Jae YOO ,  Patrick MORROW

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/068 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

公开(公告)号：US20210407997A1

公开(公告)日：2021-12-30

申请号：US16912113

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Nicole THOMAS ,  Ehren MANNEBACH ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.