公开(公告)号：US20220352032A1

公开(公告)日：2022-11-03

申请号：US17866122

申请日：2022-07-15

Applicant: INTEL CORPORATION

Inventor： Aaron D. LILAK ,  Ehren MANNEBACH ,  Anh PHAN ,  Richard E. SCHENKER ,  Stephanie A. BOJARSKI ,  Willy RACHMADY ,  Patrick R. MORROW ,  Jeffrey D. BIELEFELD ,  Gilbert DEWEY ,  Hui Jae YOO

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/48

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US20220102346A1

公开(公告)日：2022-03-31

申请号：US17547147

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Ehren MANNEBACH ,  Patrick MORROW ,  Willy RACHMADY

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/10

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

公开(公告)号：US20180226478A1

公开(公告)日：2018-08-09

申请号：US15747719

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Uygar E. AVCI ,  David L. KENCKE ,  Patrick MORROW ,  Kerryann FOLEY ,  Stephen M. CEA ,  Rishabh MEHANDRU

IPC: H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785

Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.

公开(公告)号：US20180219075A1

公开(公告)日：2018-08-02

申请号：US15747119

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20240371700A1

公开(公告)日：2024-11-07

申请号：US18774351

申请日：2024-07-16

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Ehren MANNEBACH ,  Anh PHAN ,  Richard E. SCHENKER ,  Stephanie A. BOJARSKI ,  Willy RACHMADY ,  Patrick R. MORROW ,  Jeffrey D. BIELEFELD ,  Gilbert DEWEY ,  Hui Jae YOO

IPC: H01L21/8234 ,  H01L23/48 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US20230275135A1

公开(公告)日：2023-08-31

申请号：US18131336

申请日：2023-04-05

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L27/1266 ,  H01L29/78 ,  H01L29/401 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L21/2254 ,  H01L29/66545

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20220102246A1

公开(公告)日：2022-03-31

申请号：US17547066

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Anh PHAN ,  Patrick MORROW ,  Stephanie A. BOJARSKI

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

Applicant: Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC: H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20180342532A1

公开(公告)日：2018-11-29

申请号：US15777086

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Aaron D. LILAK

IPC: H01L27/11582 ,  H01L27/108 ,  G11C11/402

CPC classification number: H01L27/11582 ,  G11C11/4023 ,  H01L27/10805 ,  H01L27/10844 ,  H01L28/00

Abstract: Embodiments of the present disclosure describe an integrated circuit that may include a first transistor on a first side of a semiconductor substrate and a second transistor on a second side of the semiconductor substrate, wherein the second side is opposite and parallel to the first side. In embodiments, the integrated circuit may further include a first capacitor positioned on the first side of the semiconductor substrate and coupled to the first transistor to form a first memory cell, and a second capacitor positioned on the second side of the semiconductor substrate and coupled to the second transistor to form a second memory cell.

公开(公告)号：US20180226492A1

公开(公告)日：2018-08-09

申请号：US15748842

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Paul B. FISCHER ,  Aaron D. LILAK ,  Stephen M. CEA

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.