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    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
    1.
    发明申请
    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220352032A1

    公开(公告)日：2022-11-03

    申请号：US17866122

    申请日：2022-07-15

    Applicant: INTEL CORPORATION

    Inventor： Aaron D. LILAK ,  Ehren MANNEBACH ,  Anh PHAN ,  Richard E. SCHENKER ,  Stephanie A. BOJARSKI ,  Willy RACHMADY ,  Patrick R. MORROW ,  Jeffrey D. BIELEFELD ,  Gilbert DEWEY ,  Hui Jae YOO

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/48

    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

    THREE DIMENSIONAL INTEGRATED CIRCUITS WITH STACKED TRANSISTORS
    2.
    发明申请
    THREE DIMENSIONAL INTEGRATED CIRCUITS WITH STACKED TRANSISTORS 审中-公开

    公开(公告)号：US20200211905A1

    公开(公告)日：2020-07-02

    申请号：US16236156

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Gilbert DEWEY ,  Aaron LILAK ,  Kimin JUN ,  Brennen MUELLER ,  Ehren MANNEBACH ,  Anh PHAN ,  Patrick MORROW ,  Hui Jae YOO ,  Jack T. KAVALIEROS

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

    Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.

    STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH
    6.
    发明公开
    STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH 审中-公开

    公开(公告)号：US20230238436A1

    公开(公告)日：2023-07-27

    申请号：US18130824

    申请日：2023-04-04

    Applicant: Intel Corporation

    Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY

    IPC: H01L29/417

    CPC classification number: H01L29/41741 ,  H01L29/41775

    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
    9.
    发明申请
    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20240371700A1

    公开(公告)日：2024-11-07

    申请号：US18774351

    申请日：2024-07-16

    Applicant: Intel Corporation

    Inventor： Aaron D. LILAK ,  Ehren MANNEBACH ,  Anh PHAN ,  Richard E. SCHENKER ,  Stephanie A. BOJARSKI ,  Willy RACHMADY ,  Patrick R. MORROW ,  Jeffrey D. BIELEFELD ,  Gilbert DEWEY ,  Hui Jae YOO

    IPC: H01L21/8234 ,  H01L23/48 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

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