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公开(公告)号:US10892225B2
公开(公告)日:2021-01-12
申请号:US16336582
申请日:2016-09-29
Applicant: Intel Corporation
Inventor: Zhiguo Qian , Kemal Aygun
IPC: H01L23/538 , H01L23/00 , H01L23/528 , H01L23/522
Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.
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公开(公告)号:US20200279793A1
公开(公告)日:2020-09-03
申请号:US16643816
申请日:2017-09-30
Applicant: Intel Corporation
Inventor: Jianyong XIE , Yidnekachew S. Mekonnen , Zhiguo Qian , Kemal Aygun
IPC: H01L23/48 , H01L25/18 , H01L23/538 , H01L23/522 , H01L23/528 , H01L23/66 , H01L23/00 , H01L25/00 , H01L23/498
Abstract: An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.
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公开(公告)号:US20200243448A1
公开(公告)日:2020-07-30
申请号:US15774306
申请日:2015-12-22
Applicant: INTEL CORPORATION
Inventor: Zhiguo Qian , Jianyong Xie , Kemal Aygun
IPC: H01L23/538 , H01L25/065 , H01L23/00 , H01L23/498 , H01L21/48
Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.
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公开(公告)号:US10607951B2
公开(公告)日:2020-03-31
申请号:US15774958
申请日:2015-12-26
Applicant: Intel Corporation
Inventor: Yu Amos Zhang , Gabriel Regalado Silva , Zhiguo Qian , Kemal Aygun
IPC: H01L23/66 , H01L23/48 , H05K1/02 , H01L23/498 , H01L21/48 , H01L23/538 , H01L23/00 , H01P3/06 , H01P11/00
Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.
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公开(公告)号:US20200021330A1
公开(公告)日:2020-01-16
申请号:US16483019
申请日:2017-03-01
Applicant: Intel Corporation
Inventor: Yidnekachew S. Mekonnen , Kemal Aygun , Henning Braunisch
Abstract: Technology for simplified multimode signaling includes determining first and second self α-terms, cross coupling α-terms, and a delay skew term. For each communication link bundled in groups, the signals can be modulated as a superposition of the signals delayed and weighted based on the first and second self α-terms, the cross coupling α-terms and the delay skew term.
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公开(公告)号:US20200014122A1
公开(公告)日:2020-01-09
申请号:US16493520
申请日:2017-03-30
Applicant: Intel Corporation
Inventor: Zhichao Zhang , Jiwei Sun , Kemal Aygun
Abstract: Length matching and phase matching between circuit paths of differing lengths is disclosed. Two signals are specified to arrive at respective path destinations at a predetermined time and with a predetermined phase. An IC provides a first electronic signal over a first conductive path to a first destination and a second electronic signal over a second conductive path to a second destination. A first slow wave structure comprises the first conductive path and a second slow wave structure comprises the second conductive path. The effective relative permittivity of the first slow wave structure is tuned such that the first electronic signal arrives at its destination at a first time and at a first phase, and the effective relative permittivity of the second slow wave structure is tuned such that the second electronic signal arrives at its destination at a second time and at a second phase.
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公开(公告)号:US10453795B2
公开(公告)日:2019-10-22
申请号:US15773896
申请日:2015-12-26
Applicant: Intel Corporation
Inventor: Yu Amos Zhang , Mathew J. Manusharow , Kemal Aygun , Mohiuddin Mazumder
IPC: H01L23/50 , H01R13/6471 , H05K1/02 , H01L23/528 , H01L23/48 , H01L23/00 , H01L23/498 , H01L23/66
Abstract: A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.
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公开(公告)号:US20190252321A1
公开(公告)日:2019-08-15
申请号:US16335029
申请日:2016-09-28
Applicant: Intel Corporation
Inventor: Henning Braunisch , Kemal Aygun , Yidnekachew S. Mekonnen
IPC: H01L23/538 , H01L23/66 , H01L25/065
CPC classification number: H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/66 , H01L25/065 , H01L25/18 , H01L2224/16235 , H01L2924/15192
Abstract: Disclosed is a signaling system. The signaling system may comprise a transmitter, a receiver, and a package interconnect. The transmitter may be configured to transmit M signals. The receiver may be configured to receive the M signals. The package interconnect may include a bundle of N wires electrically connecting the transmitter and the receiver. During operation, the N wires may be electromagnetically coupled with each other and the M signals may travel between the transmitter and the receiver on the bundle of N wires.
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公开(公告)号:US20180240788A1
公开(公告)日:2018-08-23
申请号:US15755533
申请日:2015-08-31
Applicant: Intel Corporation
Inventor: Daniel Sobieski , Kristof Darmawikarta , Sri Ranga Sai Boyapati , Merve Celikkol , Kyu Oh Lee , Kemal Aygun , Zhiguo Qian
IPC: H01L25/18 , H01L23/14 , H01L23/538 , H01L25/065 , H01L23/00
Abstract: Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.
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公开(公告)号:US10056528B1
公开(公告)日:2018-08-21
申请号:US15475219
申请日:2017-03-31
Applicant: Intel Corporation
Inventor: Zhiguo Qian , Kemal Aygun
IPC: H01L21/44 , H01L23/04 , H01L33/38 , H01L23/498 , H01L25/07 , H01L23/538 , H01L21/48
CPC classification number: H01L33/382 , H01L21/486 , H01L23/147 , H01L23/5384 , H01L23/5385 , H01L23/552 , H01L25/0655 , H01L25/073
Abstract: An interposer structure includes a plurality of front side contact interface structures for connecting the interposer structure to at least one other structure. Additionally, the interposer structure includes a plurality of back side contact interface structures for connecting the interposer structure to at least one other structure. Further, the interposer structure includes a first through substrate via and an electrically conductive shielding structure. The electrically conductive shielding structure ends before reaching a back side of the interposer substrate die and the first through substrate via is connected to the electrically conductive shielding structure at a front side of the interposer substrate die.
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