公开(公告)号：US10732217B2

公开(公告)日：2020-08-04

申请号：US16073688

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Kevin P. O'Brien ,  Kaan Oguz ,  Christopher J. Wiegand ,  Mark L. Doczy ,  Brian S. Doyle ,  MD Tofizur Rahman ,  Oleg Golonzka ,  Tahir Ghani

IPC: G01R31/28 ,  H01L43/12 ,  G01R33/09 ,  G01R31/315 ,  H01L21/66 ,  G01R33/60 ,  G01N24/10 ,  G01R35/00

Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.

公开(公告)号：US10340445B2

公开(公告)日：2019-07-02

申请号：US15755446

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/08 ,  H01L43/10 ,  H01F10/30 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include one or more electrode interface material layers disposed between a an electrode metal, such as TiN, and a seed layer of an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. The electrode interface material layers may include either or both of a Ta material layer or CoFeB material layer. In some Ta embodiments, a Ru material layer may be deposited on a TiN electrode surface, followed by the Ta material layer. In some CoFeB embodiments, a CoFeB material layer may be deposited directly on a TiN electrode surface, or a Ta material layer may be deposited on the TiN electrode surface, followed by the CoFeB material layer.

公开(公告)号：US10326075B2

公开(公告)日：2019-06-18

申请号：US15755437

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01F10/32 ,  H01F41/30 ,  G11C11/16

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.

公开(公告)号：US20180182952A1

公开(公告)日：2018-06-28

申请号：US15735395

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： Daniel R. Lamborn ,  Oleg Golonzka ,  Christopher J. Wiegand ,  Philip E. Heil ,  MD Tofizur Rahman ,  Rebecca J. Castellano ,  Tarun Bansal

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ), between first and second electrodes, comprising a dielectric layer between fixed and free layers; a dielectric film directly contacting sidewalls of the first electrode; and a metallic layer coupled to the side-walls via the dielectric film; wherein (a) a vertical axis intersects the first and second electrodes and the MTJ but not the metallic layer, (b) a first horizontal axis intersects the metallic layer, the dielectric film, and the first electrode; and (c) a second horizontal axis, between the first horizontal axis and the MTJ, intersects the dielectric film and the first electrode but not the capping layer. Other embodiments are described herein.