公开(公告)号：US20160188474A1

公开(公告)日：2016-06-30

申请号：US14583389

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Ren Wang ,  Andrew J. Herdrich ,  Yen-cheng Liu ,  Herbert H. Hum ,  Jong Soo Park ,  Christopher J. Hughes ,  Namakkal N. Venkatesan ,  Adrian C. Moga ,  Aamer Jaleel ,  Zeshan A. Chishti ,  Mesut A. Ergin ,  Jr-shian Tsai ,  Alexander W. Min ,  Tsung-yuan C. Tai ,  Christian Maciocco ,  Rajesh Sankaran

IPC: G06F12/08

CPC classification number: G06F12/0842 ,  G06F9/45558 ,  G06F12/0813 ,  G06F12/0833 ,  G06F12/0893 ,  G06F12/109 ,  G06F2009/45595 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

Abstract translation: 实现硬件/软件协同优化的方法和设备，以提高NFV和其他生产者 - 消费者工作负载之间的VM间通信的性能和能量。 该装置包括具有多级缓存层级的多核处理器，包括每个核心的L1和L2高速缓存以及共享的最后一级缓存（LLC）。 提供了一个或多个机器级指令，用于主动地将高速缓存行从低级缓存级别降级到更高的高速缓存级别，包括将高速缓存行从L1 / L2高速缓存降级到LLC。 还提供了用于在多插槽NUMA架构系统中实现硬件/软件协同优化的技术，其中高速缓存线可以被选择性地降级并被推送到远程插座中的LLC。 此外，技术是在多插槽系统中实现早期窥探的技术，以减少在远程插槽上访问高速缓存线时的延迟。

公开(公告)号：US11442760B2

公开(公告)日：2022-09-13

申请号：US15200725

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Jr-Shian Tsai ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mesut A. Ergin ,  Ravi L. Sahita ,  Andrew J. Herdrich ,  Wei Wang

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/02 ,  G06F12/109 ,  G06F12/10 ,  G11C7/10

Abstract: A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

公开(公告)号：US10356012B2

公开(公告)日：2019-07-16

申请号：US14830856

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： Alexander W. Min ,  Tsung-Yuan Tai ,  Ren Wang ,  Mesut A. Ergin ,  Jr-Shian Tsai

IPC: H04L12/931 ,  G06F9/46 ,  H04L12/947 ,  H04L12/851 ,  H04L12/721 ,  H04L12/713 ,  H04L12/741 ,  H04L12/835 ,  H04L12/26 ,  H04L12/927 ,  H04L12/813

Abstract: Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets among multiple VMs within a communications server, and between the communications server and other devices in a communications system. An apparatus may include a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through a network, and to correlate the contents to a pathway to extend through one or more of the VMs that are each configured as virtual servers of multiple virtual servers; and an interface control component to select at least one virtual network interface of each of the one or more virtual servers along the pathway to operate in a polling mode, and to select a virtual network interface of at least one virtual server of the multiple virtual servers not along the pathway to operate in a non-polling mode.

公开(公告)号：US09733987B2

公开(公告)日：2017-08-15

申请号：US14627912

申请日：2015-02-20

Applicant: INTEL CORPORATION

Inventor： Andrew J. Herdrich ,  Kapil Sood ,  Nrupal R. Jani ,  David J. Harriman ,  Mesut A. Ergin ,  Scott P. Dubal ,  Ravishankar Iyer

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/5077

Abstract: Examples may include techniques to coordinate the sharing of resources among virtual elements, including service chains, supported by a shared pool of configurable computing resources based on relative priority among the virtual element and service chains. Information including indications of the performance of the service chains and also the relative priority of the service chains may be received. The resource allocation of portions of the shared pool of configurable computing resources supporting the service chains can be adjusted based on the received performance and priority information.

公开(公告)号：US20170206177A1

公开(公告)日：2017-07-20

申请号：US14997478

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Jr-Shian Tsai ,  Ravi L. Sahita ,  Mesut A. Ergin ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Jun Nakajima ,  Edwin Verplanke ,  Barry E. Huntley ,  Tsung-Yuan C. Tai

IPC: G06F13/24 ,  G06F9/455

CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F2009/45575 ,  G06F2009/45579

Abstract: Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.

公开(公告)号：US09253793B2

公开(公告)日：2016-02-02

申请号：US13720169

申请日：2012-12-19

Applicant: Intel Corporation

Inventor： Ren Wang ,  Alexander W. Min ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Mesut A. Ergin

IPC: H04W4/00 ,  H04W72/12

CPC classification number: H04W72/1226

Abstract: Methods and systems may provide for determining quality of service (QoS) information for a job associated with an application, and determining a condition prediction for a wireless channel of a mobile platform. Additionally, the job may be scheduled for communication over the wireless channel based at least in part on the QoS information and the condition prediction. In one example, scheduling the job includes imposing a delay in the communication if the condition prediction indicates that a throughput of the wireless channel is below a threshold and the delay complies with a latency constraint of the QoS information.

Abstract translation: 方法和系统可以提供用于确定与应用相关联的作业的服务质量（QoS）信息，以及确定移动平台的无线信道的条件预测。 另外，可以至少部分地基于QoS信息和条件预测来调度该作业通过无线信道进行通信。 在一个示例中，如果条件预测指示无线信道的吞吐量低于阈值并且延迟符合QoS信息的等待时间约束，则调度该作业包括在通信中施加延迟。

公开(公告)号：US20150212564A1

公开(公告)日：2015-07-30

申请号：US14126884

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Alexander W. Min ,  Ren Wang ,  Jr-Shian Tsai ,  Mesut A. Ergin ,  Tsung-Yuan C. Tai

IPC: G06F1/32 ,  G06F13/24

CPC classification number: G06F1/32 ,  G06F1/3209 ,  G06F1/3278 ,  G06F1/329 ,  G06F13/24 ,  H04L12/12 ,  H04L49/90 ,  H04L49/9063 ,  Y02D10/157 ,  Y02D10/24 ,  Y02D50/40

Abstract: Methods and apparatus relating to adaptive interrupt coalescing for energy efficient mobile platforms are described. In one embodiment, one or more interrupts are buffered based on communication throughput. At least one of the one or more interrupts are released in response to expiration of an interrupt coalescing time period. Other embodiments are also claimed and disclosed.

Abstract translation: 描述了与能量效率移动平台的自适应中断聚结相关的方法和装置。 在一个实施例中，基于通信吞吐量来缓冲一个或多个中断。 一个或多个中断中的至少一个响应于中断合并时间段的期满被释放。 还要求和公开其它实施例。

公开(公告)号：US11513957B2

公开(公告)日：2022-11-29

申请号：US17027248

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Ren Wang ,  Andrew J. Herdrich ,  Yen-cheng Liu ,  Herbert H. Hum ,  Jong Soo Park ,  Christopher J. Hughes ,  Namakkal N. Venkatesan ,  Adrian C. Moga ,  Aamer Jaleel ,  Zeshan A. Chishti ,  Mesut A. Ergin ,  Jr-shian Tsai ,  Alexander W. Min ,  Tsung-yuan C. Tai ,  Christian Maciocco ,  Rajesh Sankaran

IPC: G06F12/0842 ,  G06F12/0893 ,  G06F12/109 ,  G06F12/0813 ,  G06F12/0831 ,  G06F9/455

Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

公开(公告)号：US11412059B2

公开(公告)日：2022-08-09

申请号：US16328865

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Huawei Xie ,  Jun Nakajima ,  David E. Cohen ,  Mesut A. Ergin ,  Wei Wang

IPC: H04L67/568 ,  H04L49/90 ,  G06F9/455

Abstract: Technologies for managing paravirtual network device queue and memory of a network computing device that includes multi-core processor, a multi-layer cache, a host, and a plurality of virtual machine instances. The host is assigned a processor core of the processor and may be configured to copy a received network packet to a last level cache of the multi-layer cache and determine one or more virtual machine instances configured to process the received network packet. Each virtual machine instance has been assigned a processor core of the processor and has been allocated a first level cache of the multi-level cache memory associated with the respective processor core. The host is additionally configured to inject an interrupt into each processor core of the determined virtual machine (s) which indicates to the virtual machine instance (s) that the received network packet is available to be processed.

公开(公告)号：US10567510B2

公开(公告)日：2020-02-18

申请号：US15722698

申请日：2017-10-02

Applicant: INTEL CORPORATION

Inventor： Mesut A. Ergin ,  Jr-Shian Tsai ,  Janet Tseng ,  Ren Wang ,  Jun Nakajima ,  Tsung-Yuan Tai

IPC: H04L12/50 ,  H04L29/08 ,  H04L12/725 ,  H04L12/721 ,  H04L12/713 ,  H04L12/835 ,  H04L12/26

Abstract: Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets between pairs of VMs within a communications server. An apparatus may include a processor component; a network interface to couple the processor component to a network; a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through the network and the communications server, and to route the set of packets through one or more virtual servers of multiple virtual servers based on the contents; and a transfer component of a first virtual server of the multiple virtual servers to determine whether to route the set of packets to the virtual switch or to transfer the set of packets to a second virtual server of the multiple virtual servers in a manner that bypasses the virtual switch based on a routing rule.