公开(公告)号：US09520877B2

公开(公告)日：2016-12-13

申请号：US14572031

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Pascal A. Meinerzhagen ,  Sandip Kundu ,  James W. Tschanz ,  Vivek K. De

IPC: H03L7/00 ,  H03K19/003 ,  H03K5/26

CPC classification number: H03K19/00323 ,  H03K5/26

Abstract: Described are apparatuses and methods for detecting or repairing minimum-delay errors. The apparatus may include a minimum-delay error detector (MDED) to receive a clock signal and a data path signal and to detect a minimum-delay error (MDE) in the data path based on the received data path signal and the clock signal. The MDE may be repaired by adjusting one or more regional clock buffers coupled to the MDED. Further, the apparatus may include minimum-delay path replicas (MDPRs) used for detecting and repairing MDEs during normal system operations. Other embodiments may be described and/or claimed.

Abstract translation: 描述了用于检测或修复最小延迟误差的装置和方法。 该装置可以包括用于接收时钟信号和数据路径信号的最小延迟误差检测器（MDED），并且基于所接收的数据路径信号和时钟信号来检测数据路径中的最小延迟误差（MDE）。 可以通过调整耦合到MDED的一个或多个区域时钟缓冲器来修复MDE。 此外，该装置可以包括用于在正常系统操作期间检测和修复MDE的最小延迟路径副本（MDPR）。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20230343389A1

公开(公告)日：2023-10-26

申请号：US17728256

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Gururaj Shamanna ,  Naveen Kumar ,  Jagadeesh Chandra Salaka ,  Pascal A. Meinerzhagen

IPC: G06F1/08 ,  G11C11/417 ,  H03K5/01 ,  H03K19/20

CPC classification number: G11C11/417 ,  G06F1/08 ,  H03K5/01 ,  H03K19/20 ,  H03K2005/00019

Abstract: An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1->0) ST CLK # based on PCLK assertion (0->1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.

公开(公告)号：US20230123514A1

公开(公告)日：2023-04-20

申请号：US17504252

申请日：2021-10-18

Applicant: Intel Corporation

Inventor： Gururaj K. Shamanna ,  Naveen Kumar M. ,  Jagadeesh Chandra Salaka ,  Pascal A. Meinerzhagen ,  Sravan K. Puchakayala ,  Iqbal Rajwani

IPC: G11C11/419 ,  H03K3/037 ,  G11C11/412

Abstract: Embodiments herein relate to optimizing the duration of a sense amp enable signal in a memory device such as SRAM. A control circuit asserts the sense amp enable signal in response to a clock signal from a replica column of the SRAM. A feedback path extends from the sense amps back to the control circuit. In one approach, a change in a feedback signal on the feedback path indicates the sense amps have all received the sense amp enable signal. In another approach, a change in a feedback signal on the feedback path indicates the sense amps have all completed their sensing operations. In some cases, a selection can be made among multiple feedback paths.

公开(公告)号：US11079830B2

公开(公告)日：2021-08-03

申请号：US15163494

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Yong Shim ,  Pascal A. Meinerzhagen

IPC: H02M3/07 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3287

Abstract: Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.

公开(公告)号：US10333379B2

公开(公告)日：2019-06-25

申请号：US15382076

申请日：2016-12-16

Applicant: Intel Corporation

Inventor： Suphachai Chai Sutanthavibul ,  Iqbal Rajwani ,  Anupama A Thaploo ,  Surya Sasi Kiran Tallapragada ,  Daivik H Bhatt ,  Lei Jiang ,  Stephen Kim ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H02M1/08 ,  H03K17/0812 ,  H03K17/687 ,  H02M3/158 ,  H02M1/088 ,  H03K19/00 ,  H02M1/00 ,  H03K17/08

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.

公开(公告)号：US10014767B2

公开(公告)日：2018-07-03

申请号：US15081445

申请日：2016-03-25

Applicant: Intel Corporation

Inventor： Jaydeep Kulkarni ,  Yong Shim ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: G05F1/10 ,  H02M3/07 ,  H03K3/03 ,  H03K5/19

CPC classification number: H02M3/07 ,  H02M2001/0032 ,  H03K3/0315 ,  H03K5/19

Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.

公开(公告)号：US09755631B2

公开(公告)日：2017-09-05

申请号：US14951343

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Yong Shim ,  Jaydeep P. Kulkarni ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: G05F1/10 ,  H03K17/081 ,  H03K17/14 ,  H03K3/037

CPC classification number: H03K17/08104 ,  H03K3/0377 ,  H03K17/145 ,  H03K19/0016

Abstract: Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.

公开(公告)号：US20170149427A1

公开(公告)日：2017-05-25

申请号：US14951343

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Yong Shim ,  Jaydeep P. Kulkarni ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H03K17/081 ,  H03K3/037 ,  H03K17/14

CPC classification number: H03K17/08104 ,  H03K3/0377 ,  H03K17/145 ,  H03K19/0016

Abstract: Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.