公开(公告)号：US11289263B2

公开(公告)日：2022-03-29

申请号：US15854460

申请日：2017-12-26

Applicant: INTEL CORPORATION

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Lauren A. Link ,  Andrew J. Brown

IPC: H01F27/28 ,  H01L23/522 ,  H01L49/02 ,  H01L23/538 ,  H01F17/00 ,  H01L21/768

Abstract: An electronic structure may be fabricated comprising an electronic substrate having at least one photo-imageable dielectric layer and an inductor embedded in the electronic substrate, wherein the inductor comprises a magnetic material layer disposed within a via formed in the at least one photo-imageable dielectric layer and an electrically conductive via extending through the magnetic material layer. The electronic structure may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.

公开(公告)号：US20200176355A1

公开(公告)日：2020-06-04

申请号：US16209861

申请日：2018-12-04

Applicant: Intel Corporation

Inventor： Robert A. May ,  Kristof Darmawikarta ,  Rahul Jain ,  Lilia May ,  Maroun Moussallem ,  Prithwish Chatterjee

IPC: H01L23/473 ,  H01L23/373 ,  H05K7/20

Abstract: A semiconductor device package structure is provided, which includes a substrate, one or more dies coupled to the substrate, and a heat pipe device. In an example, the heat pipe device may include a conduit that is at least partially embedded within the substrate. The heat pipe device may have a first region coupled to the one or more dies. In an example, the conduit may include a first path for flow of vapor from the first region to an opposing second region. The conduit may further include a second path for flow of liquid from the second region to the first region.

公开(公告)号：US20200075511A1

公开(公告)日：2020-03-05

申请号：US16119923

申请日：2018-08-31

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Rahul Jain ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

公开(公告)号：US20190221345A1

公开(公告)日：2019-07-18

申请号：US15870302

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Rahul Jain ,  Kyu Oh Lee ,  Sheng C. Li ,  Andrew J. Brown ,  Lauren A. Link

IPC: H01F1/42 ,  H01L21/56 ,  H01F27/38 ,  B32B27/38 ,  C22C45/04 ,  H01F27/28

CPC classification number: H01F1/42 ,  B32B27/38 ,  C22C45/04 ,  H01F27/2804 ,  H01F27/38 ,  H01L21/56

Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.

公开(公告)号：US11651902B2

公开(公告)日：2023-05-16

申请号：US16024715

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Andrew J. Brown ,  Prithwish Chatterjee ,  Sai Vadlamani ,  Lauren Link

IPC: H01L23/522 ,  H01G4/33 ,  H01L49/02

CPC classification number: H01G4/33 ,  H01L23/5222 ,  H01L28/40

Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.

公开(公告)号：US11495552B2

公开(公告)日：2022-11-08

申请号：US16024702

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Thomas Sounart ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prithwish Chatterjee ,  Andrew J. Brown

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

公开(公告)号：US11443885B2

公开(公告)日：2022-09-13

申请号：US15919066

申请日：2018-03-12

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas Pietambaram ,  Sandeep Gaan ,  Sri Ranga Sai Boyapati ,  Prithwish Chatterjee ,  Sameer Paital ,  Rahul Jain ,  Junnan Zhao

IPC: H01F17/00 ,  H01F17/06 ,  H01F41/04 ,  H01F27/28 ,  H01F27/24

Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.

公开(公告)号：US11189409B2

公开(公告)日：2021-11-30

申请号：US15856547

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01L21/48 ,  H01F1/20 ,  H01L23/498 ,  H01F41/02 ,  H05K1/18 ,  H01F1/37 ,  H01F1/28 ,  H01L23/00

Abstract: An inductor may be fabricated comprising a magnetic material layer and an electrically conductive via or trace extending through the magnetic material layer, wherein the magnetic material layer comprises dielectric magnetic filler particles within a carrier material. Further embodiments may include incorporating the inductor of the present description into an electronic substrate and may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.

公开(公告)号：US20210273036A1

公开(公告)日：2021-09-02

申请号：US16804317

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tarek Ibrahim ,  Prithwish Chatterjee ,  Haifa Hariri ,  Yikang Deng ,  Sheng C. Li ,  Srinivas Pietambaram

IPC: H01L49/02 ,  H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.

公开(公告)号：US20200168536A1

公开(公告)日：2020-05-28

申请号：US16202690

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： Lauren Ashley Link ,  Andrew James Brown ,  Prithwish Chatterjee ,  Sai Vadlamani ,  Ying Wang ,  Chong Zhang

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/64

Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.