公开(公告)号：US09098402B2

公开(公告)日：2015-08-04

申请号：US13725502

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Blaise Fanning ,  Mark A. Schmisseur ,  Raymond S. Tetrick ,  Robert J. Royer, Jr. ,  David B. Minturn ,  Shane Matthews

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0644 ,  G06F3/0664 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/28 ,  G06F2212/7206

Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

Abstract translation: 公开了用于配置固态驱动器（SSD）以在存储模式或存储器模式下操作的示例。 在一些示例中，可以在具有一个或多个非易失性存储器阵列的SSD的控制器处接收一个或多个配置命令。 SSD可以被配置为基于一个或多个配置命令以存储模式，存储模式或者存储模式或存储器模式的组合中的至少一个进行操作。 其他的例子被描述和要求保护。

公开(公告)号：US10649484B2

公开(公告)日：2020-05-12

申请号：US15960074

申请日：2018-04-23

Applicant: INTEL CORPORATION

Inventor： Anoop Mukker ,  Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Brian R. McFarlane

IPC: G06F1/08 ,  G06F1/12 ,  G06F13/40 ,  G06F13/42 ,  H04J3/06

Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.

公开(公告)号：US09910771B2

公开(公告)日：2018-03-06

申请号：US15396732

申请日：2017-01-02

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G06F13/42

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

公开(公告)号：US09594910B2

公开(公告)日：2017-03-14

申请号：US14229708

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Nitin V. Sarangdhar ,  Robert J. Royer, Jr. ,  Eng Hun Ooi ,  Brian R. McFarlane ,  Mukesh Kataria

IPC: G06F9/44 ,  G06F11/14 ,  G06F21/57

CPC classification number: G06F21/572 ,  G06F9/4403 ,  G06F9/4406 ,  G06F9/4411 ,  G06F11/1417 ,  G06F21/57 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/03 ,  G06F2221/033

Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.

Abstract translation: 硬件平台包括可以存储系统固件的非易失性存储设备以及用于硬件平台的主操作系统的代码。 硬件平台包括一个确定硬件平台的控制器缺乏从存储设备引导主操作系统的功能固件。 控制器从外部接口访问固件映像，该外部接口将硬件平台外部的设备连接到外部设备是固件映像源。 控制器将固件从外部设备提供给存储设备，并从配置的固件启动启动顺序。

公开(公告)号：US09535829B2

公开(公告)日：2017-01-03

申请号：US14128669

申请日：2013-07-26

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

Abstract translation: 在一个实施例中，存储器接口可以发送请求被发送的指示。 该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。 存储器接口可以经由总线将请求发送到非易失性存储器。 请求可以包括可用于标识用于存储或读取数据的位置的地址。 非易失性存储器可以从总线获取请求并处理请求。 在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。 存储器接口可以向总线授予对非易失性存储器的访问。 在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。

公开(公告)号：US11042297B2

公开(公告)日：2021-06-22

申请号：US16417310

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Blaise Fanning ,  Mark A. Schmisseur ,  Raymond S. Tetrick ,  Robert J. Royer, Jr. ,  David B. Minturn ,  Shane Matthews

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G06F13/28

Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

公开(公告)号：US10572339B2

公开(公告)日：2020-02-25

申请号：US15756039

申请日：2018-02-27

Applicant: Intel Corporation

Inventor： Robert J. Royer, Jr. ,  Blaise Fanning ,  Eng Hun Ooi

IPC: H03M13/00 ,  G06F11/10 ,  G06F12/0866 ,  G06F12/084

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

公开(公告)号：US09952619B2

公开(公告)日：2018-04-24

申请号：US14866237

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Anoop Mukker ,  Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Brian R. McFarlane

IPC: G06F1/08 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12 ,  G06F13/40 ,  G06F13/4291 ,  H04J3/0697

Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.

公开(公告)号：US09904592B2

公开(公告)日：2018-02-27

申请号：US14775848

申请日：2014-02-26

Applicant: Intel Corporation

Inventor： Robert J. Royer, Jr. ,  Blaise Fanning ,  Eng Hun Ooi

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/0866 ,  G06F12/084

CPC classification number: G06F11/1064 ,  G06F11/1048 ,  G06F12/084 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/313

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

公开(公告)号：US09678666B2

公开(公告)日：2017-06-13

申请号：US14789816

申请日：2015-07-01

Applicant: Intel Corporation

Inventor： Blaise Fanning ,  Mark A. Schmisseur ,  Raymond S. Tetrick ,  Robert J. Royer, Jr. ,  David B. Minturn ,  Shane Matthews

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0644 ,  G06F3/0664 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/28 ,  G06F2212/7206

Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.