公开(公告)号：US20210043570A1

公开(公告)日：2021-02-11

申请号：US16534027

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Kevin MCCARTHY ,  Leigh M. TRIBOLET ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.

公开(公告)号：US20200273783A1

公开(公告)日：2020-08-27

申请号：US16645744

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Robert L. SANKMAN ,  Sanka GANESAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a base die disposed on an interposer. The semiconductor package also has a plurality of dies on top of one another to form a stack on the base die. Each die has a top surface and a bottom surface that is opposite from the top surface, and each die has one or more die contacts on at least one of the top surface and the bottom surface that are each electrically coupled to at least one die contact of the base die with one or more wire bonds. The semiconductor package includes a mold layer disposed over and around the plurality of dies, the base die, and the one or more wire bonds. The base die may have a first surface area that exceeds a second surface area of the plurality of stacked dies.

公开(公告)号：US20180182696A1

公开(公告)日：2018-06-28

申请号：US15900696

申请日：2018-02-20

Applicant: INTEL CORPORATION

Inventor： Sanka GANESAN ,  Zhiguo QIAN ,  Robert L. SANKMAN ,  Krishna SRINIVASAN ,  Zhaohui ZHU

IPC: H01L23/498 ,  H01L23/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US20160248210A1

公开(公告)日：2016-08-25

申请号：US15144677

申请日：2016-05-02

Applicant: INTEL CORPORATION

Inventor： Sanka GANESAN ,  Timothy M. SWETTLEN ,  Gary B. LONG ,  Donald T. TRAN ,  Jill D. MURFIN ,  David I. AMIR

IPC: H01R43/02 ,  H01R43/20

Abstract: Stacked flex cable assemblies and their manufacture are described. One assembly includes a first flex cable and a second flex cable electrically coupled to the first flex cable. The assembly also includes a connector electrically coupled to the first flex cable. The first flex cable is positioned between the connector and the second flex cable. Other embodiments are described and claimed.

Abstract translation: 描述了堆叠的柔性电缆组件及其制造。 一个组件包括电耦合到第一柔性电缆的第一柔性电缆和第二柔性电缆。 组件还包括电连接到第一柔性电缆的连接器。 第一柔性电缆位于连接器和第二柔性电缆之间。 描述和要求保护其他实施例。

公开(公告)号：US20230089096A1

公开(公告)日：2023-03-23

申请号：US17481234

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Srinivas V. PIETAMBARAM ,  Sanka GANESAN ,  Tarek A. IBRAHIM ,  Russell MORTENSEN

IPC: H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to packages that include one or more dies that are coupled with one or more glass layers. These glass layers may be within an interposer or a patch to which the one or more dies are attached. In addition, these glass layers may be used to facilitate pitch translation between the one or more dies proximate to a first side of the glass layer and a substrate proximate to a second side of the glass layer opposite the first side, to which the one or more dies are electrically coupled. Other embodiments may be described and/or claimed.

公开(公告)号：US20230086356A1

公开(公告)日：2023-03-23

申请号：US17481237

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Sanka GANESAN ,  Ram S. VISWANATH

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to glass core-based substrates with an asymmetric number of front and back-side copper layers. In embodiments, the front and/or backside copper layers may be referred to as stack ups or as buildup layers on the glass core substrate. Embodiments may allow lower overall substrate layer counts by allowing for more front side layers where the signal routing may typically be highest, without requiring a matching, or symmetric, number of backside copper layers. Other embodiments may be described and/or claimed.

公开(公告)号：US20200051899A1

公开(公告)日：2020-02-13

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Sanka GANESAN ,  Pilin LIU ,  Shawna LIFF ,  Sri Chaitra CHAVALI ,  Sandeep GAAN ,  Jimin YAO ,  Aastha UPPAL

IPC: H01L23/498 ,  H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US20190279938A1

公开(公告)日：2019-09-12

申请号：US16461316

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Vipul Vijay MEHTA ,  Eric Jin LI ,  Sanka GANESAN ,  Debendra MALLIK ,  Robert Leon SANKMAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

公开(公告)号：US20190172778A1

公开(公告)日：2019-06-06

申请号：US16261475

申请日：2019-01-29

Applicant: INTEL CORPORATION

Inventor： Sanka GANESAN ,  Zhiguo QIAN ,  Robert L. SANKMAN ,  Krishna SRINIVASAN ,  Zhaohui ZHU

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/50

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US20160284635A1

公开(公告)日：2016-09-29

申请号：US15174921

申请日：2016-06-06

Applicant: INTEL CORPORATION

Inventor： Sanka GANESAN ,  Zhiguo QIAN ,  Robert L. SANKMAN ,  Krishna SRINIVASAN ,  Zhaohui ZHU

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Abstract translation: 描述了包括形成互连结构的电子组件和方法。 在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。 该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。 描述和要求保护其他实施例。