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公开(公告)号:US20240136326A1
公开(公告)日:2024-04-25
申请号:US18399189
申请日:2023-12-28
Applicant: Intel Corporation
Inventor: Wei LI , Edvin CETEGEN , Nicholas S. HAEHN , Ram S. VISWANATH , Nicholas NEAL , Mitul MODI
IPC: H01L25/065 , H01L21/48 , H01L21/56 , H01L21/78 , H01L23/00 , H01L23/31 , H01L23/498
CPC classification number: H01L25/0652 , H01L21/486 , H01L21/561 , H01L21/78 , H01L23/3128 , H01L23/49827 , H01L24/16 , H01L2224/16225
Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
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公开(公告)号:US20230086356A1
公开(公告)日:2023-03-23
申请号:US17481237
申请日:2021-09-21
Applicant: Intel Corporation
Inventor: Andrew COLLINS , Srinivas V. PIETAMBARAM , Tarek A. IBRAHIM , Sanka GANESAN , Ram S. VISWANATH
IPC: H01L23/498 , H01L21/48
Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to glass core-based substrates with an asymmetric number of front and back-side copper layers. In embodiments, the front and/or backside copper layers may be referred to as stack ups or as buildup layers on the glass core substrate. Embodiments may allow lower overall substrate layer counts by allowing for more front side layers where the signal routing may typically be highest, without requiring a matching, or symmetric, number of backside copper layers. Other embodiments may be described and/or claimed.
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公开(公告)号:US20240145395A1
公开(公告)日:2024-05-02
申请号:US18406018
申请日:2024-01-05
Applicant: Intel Corporation
Inventor: MD Altaf HOSSAIN , Ankireddy NALAMALPU , Dheeraj SUBBAREDDY , Robert SANKMAN , Ravindranath V. MAHAJAN , Debendra MALLIK , Ram S. VISWANATH , Sandeep B. SANE , Sriram SRINIVASAN , Rajat AGARWAL , Aravind DASU , Scott WEBER , Ravi GUTALA
IPC: H01L23/538 , H01L23/00 , H01L25/18
CPC classification number: H01L23/5385 , H01L23/5386 , H01L24/16 , H01L24/17 , H01L25/18 , H01L23/481 , H01L2224/16225
Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
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公开(公告)号:US20230238355A1
公开(公告)日:2023-07-27
申请号:US18127539
申请日:2023-03-28
Applicant: Intel Corporation
Inventor: Wei LI , Edvin CETEGEN , Nicholas S. HAEHN , Ram S. VISWANATH , Nicholas NEAL , Mitul MODI
IPC: H01L25/065 , H01L23/31 , H01L23/498 , H01L21/56 , H01L21/78 , H01L21/48 , H01L23/00
CPC classification number: H01L25/0652 , H01L21/78 , H01L21/486 , H01L21/561 , H01L23/3128 , H01L23/49827 , H01L24/16 , H01L2224/16225
Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
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公开(公告)号:US20210104490A1
公开(公告)日:2021-04-08
申请号:US16596367
申请日:2019-10-08
Applicant: Intel Corporation
Inventor: Wei LI , Edvin CETEGEN , Nicholas S. HAEHN , Ram S. VISWANATH , Nicholas NEAL , Mitul MODI
IPC: H01L25/065 , H01L23/31 , H01L23/498 , H01L23/00 , H01L21/56 , H01L21/78 , H01L21/48
Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
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公开(公告)号:US20200258759A1
公开(公告)日:2020-08-13
申请号:US16635539
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Wilfred GOMES , Ravindranath V. MAHAJAN , Ram S. VISWANATH
IPC: H01L21/48 , H01L23/31 , H01L21/56 , H01L23/367
Abstract: Techniques and mechanisms for conducting heat with a packaged integrated circuit (IC) device. In an embodiment, the IC device comprises a package substrate and one or more IC dies coupled thereto, where a thermal conductor of the IC device extends through the package substrate. A thermal conductivity of the thermal conductor is more than 20 Watts per meter per degree Kelvin (W/mK). In another embodiment, thermal conductor further extends at least partially through a mold compound disposed on the one or more IC dies.
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公开(公告)号:US20200211969A1
公开(公告)日:2020-07-02
申请号:US16235879
申请日:2018-12-28
Applicant: Intel Corporation
Inventor: MD Altaf HOSSAIN , Ankireddy NALAMALPU , Dheeraj SUBBAREDDY , Robert SANKMAN , Ravindranath V. MAHAJAN , Debendra MALLIK , Ram S. VISWANATH , Sandeep B. SANE , Sriram SRINIVASAN , Rajat AGARWAL , Aravind DASU , Scott WEBER , Ravi GUTALA
IPC: H01L23/538 , H01L25/18 , H01L23/00
Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
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公开(公告)号:US20200066641A1
公开(公告)日:2020-02-27
申请号:US16305012
申请日:2016-07-02
Applicant: Intel Corporation
Inventor: Kemal AYGUN , Richard J. DISCHLER , Jeff C. MORRISS , Zhiguo QIAN , Wilfred GOMES , Yu Amos ZHANG , Ram S. VISWANATH , Rajasekaran SWAMINATHAN , Sriram SRINIVASAN , Yidnekachew S. MEKONNEN , Sanka GANESAN , Eduard ROYTMAN , Mathew J. MANUSHAROW
IPC: H01L23/538 , H01L25/065 , H01L23/522 , H01L23/528 , H01L23/00 , H01L23/60
Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
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