公开(公告)号：US20230101760A1

公开(公告)日：2023-03-30

申请号：US17485225

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Uygar E. AVCI ,  Scott B. CLENDENNING ,  Chelsey DOROW ,  Sudarat LEE ,  Kirby MAXEY ,  Carl H. NAYLOR ,  Tristan A. TRONIC ,  Shriram SHIVARAMAN ,  Ashish Verma PENUMATCHA

IPC: H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L23/48 ,  H01L29/786

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a first transistor on a first level, and a second transistor on a second level above the first level. In an embodiment, an insulating layer is between the first level and the second level, and a via passes through the insulating layer, and electrically couples the first transistor to the second transistor. In an embodiment, the first transistor and the second transistor comprise a first channel, and a second channel over the first channel. In an embodiment, the first second transistor further comprise a gate structure between the first channel and the second channel, a source contact on a first end of the first channel and the second channel, and a drain contact on a second end of the first channel and the second channel.

公开(公告)号：US20230097641A1

公开(公告)日：2023-03-30

申请号：US17485311

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Christopher M. NEUMANN ,  Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L27/11514 ,  H01L27/11504 ,  H01L21/768

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, ferroelectric three-dimensional (3D) memory architectures. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220199799A1

公开(公告)日：2022-06-23

申请号：US17131706

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Chelsey DOROW ,  Carl NAYLOR ,  Kirby MAXEY ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Ashish Verma PENUMATCHA ,  Chia-Ching LIN ,  Shriram SHIVARAMAN ,  Sudarat LEE

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

Abstract: Thin film transistors having boron nitride integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first gate stack above a substrate. A 2D channel material layer is above the first gate stack. A second gate stack is above the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack and in contact with the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack and in contact with the 2D channel material layer. A hexagonal boron nitride (hBN) layer is included between the first gate stack and the 2D channel material layer, between the second gate stack and the 2D channel material layer, or both.

公开(公告)号：US20210391478A1

公开(公告)日：2021-12-16

申请号：US16902069

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Carl NAYLOR ,  Ashish Verma PENUMATCHA ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/24

Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.

公开(公告)号：US20210167182A1

公开(公告)日：2021-06-03

申请号：US16700757

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Ashish Verma PENUMATCHA ,  Sou-Chi CHANG ,  Devin MERRILL ,  I-Cheng TUNG ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Chia-Ching LIN ,  Owen LOH ,  Shriram SHIVARAMAN ,  Eric Charles MATTSON

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：US20210111179A1

公开(公告)日：2021-04-15

申请号：US16599422

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Ashish Verma PENUMATCHA ,  Nazila HARATIPOUR ,  Uygar E. AVCI

IPC: H01L27/11514 ,  H01L49/02 ,  H01L27/11507 ,  G11C11/22 ,  H01L27/11504

Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.

公开(公告)号：US20240186416A1

公开(公告)日：2024-06-06

申请号：US18414290

申请日：2024-01-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L21/02568 ,  H01L21/0262

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20240114697A1

公开(公告)日：2024-04-04

申请号：US17958279

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Sourav DUTTA ,  Uygar E. AVCI

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Embodiments disclosed herein include a memory device. In an embodiment, the memory device comprises a first transistor, where the first transistor is an access transistor to write data. In an embodiment, the memory device further comprises a ferroelectric capacitor for storing data. In an embodiment, the memory device further comprises a second transistor, where the second transistor is a sense transistor to read the data stored on the ferroelectric capacitor.

公开(公告)号：US20230101604A1

公开(公告)日：2023-03-30

申请号：US17485314

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Tanay GOSAVI ,  Shriram SHIVARAMAN ,  Carl H. NAYLOR ,  Chelsey DOROW ,  Ian A. YOUNG ,  Nazila HARATIPOUR ,  Kevin P. O'BRIEN

IPC: H01L29/76 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/24

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional (3D) memory devices with transition metal dichalcogenide (TMD) channels. Other embodiments may be disclosed or claimed.

公开(公告)号：US20230101111A1

公开(公告)日：2023-03-30

申请号：US17485317

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Uygar E. AVCI ,  Sarah ATANASOV ,  Jason PECK ,  Christopher M. NEUMANN

IPC: H01L27/11514 ,  H01L27/11507

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional ferroelectric random access memory (3D FRAM) devices with a sense transistor coupled to a plurality of capacitors to (among other things) help improve signal levels and scaling. Other embodiments may be disclosed or claimed.