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    Apparatus and method for improved lock elision techniques
    15.
    发明授权
    Apparatus and method for improved lock elision techniques 有权
    用于改进锁定检测技术的装置和方法

    公开(公告)号：US09588801B2

    公开(公告)日：2017-03-07

    申请号：US14024451

    申请日：2013-09-11

    申请人： Intel Corporation

    发明人： Irina Calciu ,  Justin E Gottschlich ,  Tatiana Shpeisman ,  Gilles A Pokam

    IPC分类号： G06F9/30 ,  G06F9/46 ,  G06F12/14 ,  G06F9/52

    CPC分类号： G06F9/467 ,  G06F9/30181 ,  G06F9/526 ,  G06F12/1466

    摘要： An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For example, a method in accordance with one embodiment comprises: waiting to execute a speculative critical section of program code until a lock is freed by a current transaction; responsively executing the speculative critical section to completion upon detecting that the lock has been freed, regardless of whether the lock is held by another transaction during the execution of the speculative critical section; once execution of the speculative critical section is complete, determining whether the lock is taken; and if the lock is not taken, then committing the speculative critical section and, if the lock is taken, then aborting the speculative critical section.

    摘要翻译： 一种用于提高在事务存储架构内执行投机关键部分的效率的装置和方法。 例如，根据一个实施例的方法包括：等待执行程序代码的推测性临界部分，直到当前事务释放锁定为止; 在检测到锁已经被释放时响应地执行推测性关键部分以完成，而不管在推测性关键部分的执行期间锁是否被另一事务持有; 一旦投机关键部分的执行完成，确定是否采取锁定; 如果不采取锁定，则提交投机性关键部分，如果采取锁定，则中止推测性关键部分。

    TRANSACTIONAL MEMORY MANAGEMENT TECHNIQUES
    16.
    发明申请
    TRANSACTIONAL MEMORY MANAGEMENT TECHNIQUES 审中-公开

    公开(公告)号：US20160371036A1

    公开(公告)日：2016-12-22

    申请号：US15160786

    申请日：2016-05-20

    申请人： Intel Corporation

    发明人： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman

    IPC分类号： G06F3/06 ,  G06F9/46

    CPC分类号： G06F3/0659 ,  G06F3/0613 ,  G06F3/067 ,  G06F3/0673 ,  G06F9/44 ,  G06F9/466 ,  G06F9/467 ,  G06F12/0813

    摘要： Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.

    Managed runtime extensions to reduce power consumption in devices with hybrid memory
    17.
    发明授权
    Managed runtime extensions to reduce power consumption in devices with hybrid memory 有权
    受管理的运行时扩展，以减少具有混合内存的设备的功耗

    公开(公告)号：US09507714B2

    公开(公告)日：2016-11-29

    申请号：US14227432

    申请日：2014-03-27

    申请人： Intel Corporation

    发明人： Stephan A. Herhut ,  Richard L. Hudson ,  Tatiana Shpeisman

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0276 ,  G06F12/0238 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/205 ,  G06F2212/7202 ,  G06F2212/7205 ,  Y02D10/13

    摘要： Systems and methods may provide for identifying an object in a managed runtime environment and determining an age of the object at a software level of the managed runtime environment. Additionally, the object may be selectively allocated in one of a dynamic random access memory (DRAM) or a non-volatile random access memory (NVRAM) based at least in part on the age of the object. In one example, the data type of the object is also determined, wherein the object is selectively allocated further based on the data type.

    摘要翻译： 系统和方法可以提供用于识别被管理的运行时环境中的对象并且在所管理的运行时环境的软件级别确定对象的年龄。 另外，可以至少部分地基于对象的年龄，将对象选择性地分配在动态随机存取存储器（DRAM）或非易失性随机存取存储器（NVRAM）之一中。 在一个示例中，还确定对象的数据类型，其中基于数据类型有选择地分配对象。

    Transactional memory management techniques
    18.
    发明授权
    Transactional memory management techniques 有权
    事务性内存管理技术

    公开(公告)号：US09361152B2

    公开(公告)日：2016-06-07

    申请号：US14129936

    申请日：2013-07-15

    申请人： Intel Corporation

    发明人： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman

    IPC分类号： G06F12/10 ,  G06F9/46 ,  G06F9/44 ,  G06F12/08 ,  G06F3/06

    CPC分类号： G06F3/0659 ,  G06F3/0613 ,  G06F3/067 ,  G06F3/0673 ,  G06F9/44 ,  G06F9/466 ,  G06F9/467 ,  G06F12/0813

    摘要： Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.

    摘要翻译： 描述了改进的事务性内存管理技术。 在一个实施例中，例如，设备可以包括处理器元件，用于由处理器元件执行以根据事务存储器进程同时执行软件事务和硬件事务的执行部件，用于由处理器元件执行的跟踪部件 激活全局锁以指示软件事务正在执行;以及最终化组件，用于由处理器元件执行以提交软件事务，并且在执行软件事务完成时停用全局锁定，终止组件中止硬件 当执行硬件事务完成时，全局锁活动时的事务。 描述和要求保护其他实施例。

    METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM
    19.
    发明申请
    METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM 审中-公开
    在异位平台上配置共享点的方法和装置

    公开(公告)号：US20150186273A1

    公开(公告)日：2015-07-02

    申请号：US14513065

    申请日：2014-10-13

    申请人： Intel Corporation

    发明人： Yang Ni ,  Rajkishore Barik ,  Ali-Reza Adl-Tabatabai ,  Tatiana Shpeisman ,  Jayanth N. Rao ,  Ben J. Ashbaugh ,  Tomasz Janczak

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0806 ,  G06F15/167 ,  G06T1/60

    摘要： A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

    摘要翻译： 一种促进异构平台中的共享指针的方法和装置。 在本发明的一个实施例中，异构或非均匀平台包括但不限于中央处理核心或单元，图形处理核心或单元，数字信号处理器，接口模块和任何其他形式的 处理核心。 异构平台具有促进共享指向CPU和GPU共享的存储器的位置的逻辑。 通过在异构平台中共享指针，可以简化异构平台中不同核心之间的数据或信息共享。