公开(公告)号：US09207880B2

公开(公告)日：2015-12-08

申请号：US14142734

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Victor W. Lee

IPC: G06F3/06 ,  G06F9/38 ,  G06F13/28

CPC classification number: G06F3/0688 ,  G06F3/0604 ,  G06F3/0638 ,  G06F9/3004 ,  G06F9/30167 ,  G06F9/38 ,  G06F9/3832 ,  G06F13/28 ,  G06F2003/0695

Abstract: A processor of an aspect includes an on-die programmable architecturally-visible storage. The processor also includes a decode unit to receive a data access instruction of an instruction set of the processor. The data access instruction to indicate a data address that is to be associated with data to be stored in the on-die programmable architecturally-visible storage, to indicate a data size associated with the data to be stored in the on-die programmable architecturally-visible storage, and to indicate a destination storage location of the processor. An execution unit is coupled with the decode unit and the on-die programmable architecturally-visible storage. The execution unit is on-die with the on-die programmable storage. The execution unit is operable, in response to the data access instruction, to store the data, which is associated with the data address and the data size, in the destination storage location that is to be indicated by the instruction.

Abstract translation: 一个方面的处理器包括可在模块上可编程的架构可见存储器。 处理器还包括用于接收处理器的指令集的数据访问指令的解码单元。 数据访问指令，用于指示要与要存储在片上可编程结构可见存储器中的数据相关联的数据地址，以指示与待存储在片上可编程结构可见存储器中的数据相关联的数据大小， 可见存储，并指示处理器的目的地存储位置。 执行单元与解码单元和片上可编程结构可见存储器耦合。 执行单元与片上可编程存储器在一起。 执行单元响应于数据访问指令可操作地将与数据地址和数据大小相关联的数据存储在由指令指示的目的地存储单元中。

公开(公告)号：US10579378B2

公开(公告)日：2020-03-03

申请号：US14228016

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Edward T. Grochowski ,  Victor W. Lee ,  Sergey A. Rozhkov ,  Boris A. Babayan

IPC: G06F9/30

Abstract: An apparatus and method are described for executing instructions using a predicate register. For example, one embodiment of a processor comprises: a register set including a predicate register to store a set of predicate condition bits, the predicate condition bits specifying whether results of a particular predicated instruction sequence are to be retained or discarded; and predicate execution logic to execute a first predicate instruction to indicate a start of a new predicated instruction sequence by copying a condition value from a processor control register in the register set to the predicate register. In a further embodiment, the predicate condition bits in the predicate register are to be shifted in response to the first predicate instruction to free space within the predicate register for the new condition value associated with the new predicated instruction sequence.

公开(公告)号：US20190265777A1

公开(公告)日：2019-08-29

申请号：US16288580

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC: G06F1/3287 ,  G06F9/50 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F1/324

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US10234930B2

公开(公告)日：2019-03-19

申请号：US14621709

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/50

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US09910481B2

公开(公告)日：2018-03-06

申请号：US14621731

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Daehyun Kim ,  Yuxin Bai ,  Shihao Ji ,  Sheng Li ,  Dhiraj D. Kalamkar ,  Naveen K. Mellempudi

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5088 ,  G06F9/5094 ,  Y02D10/124 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/22 ,  Y02D10/32

Abstract: In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.

公开(公告)号：US10152325B2

公开(公告)日：2018-12-11

申请号：US15426963

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Jong Soo Park

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/44 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F9/54

Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.

公开(公告)号：US10146286B2

公开(公告)日：2018-12-04

申请号：US14995263

申请日：2016-01-14

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Yuxin Bai

IPC: G06F1/00 ,  G06F1/28 ,  G06N99/00 ,  G06F1/32 ,  G06F1/30

Abstract: In one embodiment, A processor includes a logic to receive performance monitoring information from at least some of a plurality of cores and determine, according to a power management model, a performance state for one or more of the plurality of cores based on the performance monitoring information, and a second logic to receive the performance monitoring information and dynamically update the power management model according to a reinforcement learning process. Other embodiments are described and claimed.

公开(公告)号：US09244677B2

公开(公告)日：2016-01-26

申请号：US13630147

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Nalini Vasudevan ,  Jayashankar Bharadwaj ,  Christopher J. Hughes ,  Milind B. Girkar ,  Mark J Charney ,  Robert Valentine ,  Victor W. Lee ,  Daehyun Kim ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/44 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F8/443 ,  G06F8/433 ,  G06F8/452 ,  G06F8/70 ,  G06F9/30036 ,  G06F9/38 ,  G06F9/3836

Abstract: Loop vectorization methods and apparatus are disclosed. An example method includes setting a dynamic adjustment value of a vectorization loop; executing the vectorization loop to vectorize a loop by grouping iterations of the loop into one or more vectors; identifying a dependency between iterations of the loop as; and setting the dynamic adjustment value based on the identified dependency.

Abstract translation: 公开了环向量化方法和装置。 示例性方法包括设置矢量化循环的动态调整值; 执行向量化循环以通过将循环的迭代分组为一个或多个向量来矢量化循环; 识别循环迭代之间的依赖关系; 并且基于所识别的依赖关系来设置动态调整值。

公开(公告)号：US09069671B2

公开(公告)日：2015-06-30

申请号：US14337174

申请日：2014-07-21

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。

公开(公告)号：US08799577B2

公开(公告)日：2014-08-05

申请号：US13934198

申请日：2013-07-02

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。