中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

31 records (took 0.024 seconds)

    NON-CRYPTOGRAPHIC HASHING USING CARRY-LESS MULTIPLICATION
    13.
    发明申请
    NON-CRYPTOGRAPHIC HASHING USING CARRY-LESS MULTIPLICATION 有权

    公开(公告)号：US20230015000A1

    公开(公告)日：2023-01-19

    申请号：US17902180

    申请日：2022-09-02

    Applicant: Intel Corporation

    Inventor： Gregory B. TUCKER ,  Vinodh GOPAL

    IPC: H04L9/06 ,  G06F9/38 ,  G06F9/30

    Abstract: Non-cryptographic hashing using carry-less multiplication and associated methods, software, and apparatus. Under one aspect, the disclosed hash solution expands on CRC technology that updates a polynomial expansion and final reduction, to use initialization (init), update and finalize stages with extended seed values. The hash solutions operate on input data partitioned into multiple blocks comprising sequences of byte data, such as ASCII characters. During multiple rounds of an update stage, operations are performed on sub-blocks of a given block in parallel including carry-less multiplication and shuffle operations. During a finalize stage, multiple SHA or carry-less multiplication operations are performed on data output following a final round of the update stage.

    PROCESS-BASED MULTI-KEY TOTAL MEMORY ENCRYPTION
    16.
    发明申请
    PROCESS-BASED MULTI-KEY TOTAL MEMORY ENCRYPTION 有权

    公开(公告)号：US20210149704A1

    公开(公告)日：2021-05-20

    申请号：US17127729

    申请日：2020-12-18

    Applicant: Intel Corporation

    Inventor： Wajdi FEGHALI ,  Vinodh GOPAL ,  Kirk S. YAP ,  Sean GULLEY ,  Raghunandan MAKARAM

    IPC: G06F9/455 ,  G06F12/14 ,  H04L9/08

    Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.

    INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS SECURE HASH ALGORITHMS
    17.
    发明申请
    INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS SECURE HASH ALGORITHMS 审中-公开

    公开(公告)号：US20200280432A1

    公开(公告)日：2020-09-03

    申请号：US16807021

    申请日：2020-03-02

    Applicant: Intel Corporation

    Inventor： Gilbert M. WOLRICH ,  Kirk S. YAP ,  Vinodh GOPAL ,  James D. GUILFORD

    IPC: H04L9/06 ,  G06F21/64 ,  G06F9/30 ,  G06F21/72 ,  G06F21/60

    Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

Patent Agency Ranking