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公开(公告)号：US20220207147A1
公开(公告)日：2022-06-30
申请号：US17134343
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Carlos Rozas , Fangfei Liu , Xiang Zou , Francis McKeen , Jason W. Brandt , Joseph Nuzman , Alaa Alameldeen , Abhishek Basak , Scott Constable , Thomas Unterluggauer , Asit Mallick , Matthew Fernandez
Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a register hardening instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the register hardening instruction.
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公开(公告)号：US09875102B2
公开(公告)日：2018-01-23
申请号：US15386615
申请日：2016-12-21
Applicant: Intel Corporation
Inventor： Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju V. Patel , Jason W. Brandt , Anil Aggarwal , John L. Reid
CPC classification number: G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3861 , G06F9/3877 , G06F9/3885 , G06F9/461
Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
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公开(公告)号：US09766891B2
公开(公告)日：2017-09-19
申请号：US15166469
申请日：2016-05-27
Applicant: Intel Corporation
Inventor： Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju V. Patel , Jason W. Brandt , Anil Aggarwal , John L. Reid
CPC classification number: G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3861 , G06F9/3877 , G06F9/3885 , G06F9/461
Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
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公开(公告)号：US09383997B2
公开(公告)日：2016-07-05
申请号：US13914830
申请日：2013-06-11
Applicant: Intel Corporation
Inventor： Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju V. Patel , Jason W. Brandt , Anil Aggarwal , John L. Reid
CPC classification number: G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3861 , G06F9/3877 , G06F9/3885 , G06F9/461
Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
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公开(公告)号：US20250021849A1
公开(公告)日：2025-01-16
申请号：US18220212
申请日：2023-07-10
Applicant: Intel Corporation
Inventor： Sahar Daraeizadeh , Todor Mladenov , Xiang Zou , Anne Matsuura
IPC: G06N10/20
Abstract: Apparatus and method for a quantum control processor. For example, one embodiment of a QCP comprises: instruction fetch logic to fetch instructions from a memory, the instructions including quantum instructions; decode logic to decode the quantum instructions into a first plurality of quantum microoperations; translation logic translate the first plurality of quantum microoperations into a second plurality of quantum microoperations based on characteristics of a plurality of quantum controller cores coupled to the quantum control processor; and issue logic to synchronously issue the second plurality of quantum microoperations in parallel to the plurality of quantum controller cores.
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Patent Agency Ranking
公开(公告)号：US11704588B2
公开(公告)日：2023-07-18
申请号：US16144963
申请日：2018-09-27
Applicant: Intel Corporation
Inventor： Xiang Zou , Justin Hogaboam
CPC classification number: G06N10/70 , G06F9/22 , G06F9/3017 , G06F9/30101 , G06F9/3877
Abstract: Apparatus and method for injected spin echo sequences in a quantum processor. For example, one embodiment of a processor includes a decoder to decode quantum instructions to generate quantum microoperations (uops) and to decode non-quantum instructions to generate non-quantum uops, execution circuitry to execute the quantum uops and non-quantum uops, and a corrective sequence data structure to identify and/or store corrective sets of uops for one or more of the quantum instructions. The decoder is to query the corrective sequence data structure upon receiving a first quantum instruction to determine if one or more corrective uops exist, and if the one or more corrective uops exist, the decoder is to submit the one or more corrective uops for execution by the execution circuitry.
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公开(公告)号：US11010166B2
公开(公告)日：2021-05-18
申请号：US15087854
申请日：2016-03-31
Applicant: Intel Corporation
Inventor： Debabrata Mohapatra , Perry H. Wang , Xiang Zou , Sang Kyun Kim , Deepak A. Mathaikutty , Gautham N. Chinya
Abstract: A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.
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18.发明申请公开(公告)号：US20200242208A1
公开(公告)日：2020-07-30
申请号：US16261113
申请日：2019-01-29
Applicant: Intel Corporation
Inventor： Sahar Daraeizadeh , Anne Matsuura , Xiang Zou , Sonika Johri
Abstract: Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.
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公开(公告)号：US09910796B2
公开(公告)日：2018-03-06
申请号：US13844343
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Hong Wang , Per Hammarlund , Xiang Zou , John P. Shen , Xinmin Tian , Milind Girkar , Perry H. Wang , Piyush N. Desai
CPC classification number: G06F13/24 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3851 , G06F9/4843 , G06F11/3024 , G06F11/348 , G06F12/0875 , G06F2201/86 , G06F2201/88 , G06F2201/885 , G06F2212/452
Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.
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公开(公告)号：US20170286117A1
公开(公告)日：2017-10-05
申请号：US15087854
申请日：2016-03-31
Applicant: Intel Corporation
Inventor： Debabrata Mohapatra , Perry H. Wang , Xiang Zou , Sang Kyun Kim , Deepak A. Mathaikutty , Gautham N. Chinya
IPC: G06F9/30
CPC classification number: G06F9/30145 , G06F9/30076 , G06F9/30101 , G06F9/30123 , G06F9/30189 , G06F9/3836 , G06F9/3873
Abstract: A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.
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