Metal-insulator-semiconductor (MIS) contact with controlled defect density
    11.
    发明申请
    Metal-insulator-semiconductor (MIS) contact with controlled defect density 审中-公开
    金属 - 绝缘体 - 半导体(MIS)接触具有受控的缺陷密度

    公开(公告)号:US20150380309A1

    公开(公告)日:2015-12-31

    申请号:US14315718

    申请日:2014-06-26

    Abstract: Metal-insulator-semiconductor (MIS) contacts for germanium and its alloys include insulator layers of oxygen-deficient metal oxide deposited by atomic layer deposition (ALD). The oxygen deficiency reduces the tunnel barrier resistance of the insulator layer while maintaining the layer's ability to prevent Fermi-level pinning at the metal/semiconductor interface. The oxygen deficiency is controlled by optimizing one or more ALD parameters such as shortened oxidant pulses, use of less-reactive oxidants such as water, heating the substrate during deposition, TMA “cleaning” of native oxide before deposition, and annealing after deposition. Secondary factors include reduced process-chamber pressure, cooled oxidant, and shortened pulses of the metal precursor.

    Abstract translation: 用于锗及其合金的金属 - 绝缘体 - 半导体(MIS)触点包括通过原子层沉积(ALD)沉积的缺氧金属氧化物的绝缘体层。 缺氧会降低绝缘体层的隧道势垒阻力,同时保持层在金属/半导体界面处防止费米能级钉扎的能力。 通过优化一个或多个ALD参数,例如缩短的氧化剂脉冲,使用较少反应性的氧化剂例如水,在沉积期间加热衬底,在沉积之前对自然氧化物进行TMA“清洁”,以及沉积后的退火来优化一个或多个ALD参数来控制氧缺乏。 次要因素包括降低的处理室压力,冷却的氧化剂和金属前体的缩短的脉冲。

    PVD-ALD-CVD hybrid HPC for work function material screening
    13.
    发明申请
    PVD-ALD-CVD hybrid HPC for work function material screening 审中-公开
    PVD-ALD-CVD混合HPC用于工作功能材料筛选

    公开(公告)号:US20140162384A1

    公开(公告)日:2014-06-12

    申请号:US13706648

    申请日:2012-12-06

    Inventor: Amol Joshi

    CPC classification number: H01L22/14 H01L22/12 H01L22/20

    Abstract: A substrate is provided wherein the substrate includes a number of site-isolated regions (SIRs). At least one material is deposited using PVD on a sub-set of the SIRs. At least one of the material or the process conditions are varied in a combinatorial manner across the sub-set of SIRs. Next, at least one material is deposited using ALD on a sub-set of the SIRs. At least one of the material or the process conditions are varied in a combinatorial manner across the sub-set of SIRs. Next, a material is deposited across the entire substrate using CVD. Each device within each of the SIRs is evaluated for at least one of an electric property or a material property.

    Abstract translation: 提供了一种衬底,其中衬底包括许多位置隔离区域(SIR)。 在SIR的子集上使用PVD沉积至少一种材料。 材料或工艺条件中的至少一个以跨组合的SIR组合的方式变化。 接下来,使用ALD在SIR的子集上沉积至少一种材料。 材料或工艺条件中的至少一个以跨组合的SIR组合的方式变化。 接下来,使用CVD将材料沉积在整个基板上。 对每个SIR中的每个设备进行电特性或材料特性中的至少一个的评估。

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