公开(公告)号：US20180090428A1

公开(公告)日：2018-03-29

申请号：US15817787

申请日：2017-11-20

Applicant: International Business Machines Corporation

Inventor： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

IPC: H01L23/498 ,  H01L23/473 ,  H01L25/065 ,  H01L23/46

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L23/34 ,  H01L23/46 ,  H01L23/473 ,  H01L23/488 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15159 ,  H01L2924/3011

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in the casing, and for forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. Opposing edges of the upper card are located between vertical planes defined by the outer sidewalls of the upper portion of the casing.

公开(公告)号：US09905505B2

公开(公告)日：2018-02-27

申请号：US14924256

申请日：2015-10-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

IPC: H01L23/34 ,  H01L23/498 ,  H01L23/473 ,  H01L25/065 ,  H01L23/46

CPC classification number: H01L23/49827 ,  H01L23/46 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15159 ,  H01L2924/3011

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in an upper surface of the casing, and forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

公开(公告)号：US09252072B2

公开(公告)日：2016-02-02

申请号：US14096729

申请日：2013-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

IPC: H01L23/46 ,  H01L23/473 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/46 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15159 ,  H01L2924/3011

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

Abstract translation: 一种组件，包括集成电路的芯片，包括集成电路的壳体，该集成电路包括多个有源元件，并且具有形成在芯片的另一侧的芯片侧的上部和形成在芯片的另一侧的下部，多个贯通晶片通孔（TWV ），用于将芯片的集成电路与壳体的集成电路电连接，以及连接到壳体的卡，用于将壳体电连接到系统板。

公开(公告)号：US08689152B2

公开(公告)日：2014-04-01

申请号：US13783438

申请日：2013-03-04

Applicant: International Business Machines Corporation

Inventor： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Paul D. Kartschoke ,  Stephen E. Luce ,  Anthony K. Stamper

IPC: G06F17/50 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L21/30 ,  H01L21/46

CPC classification number: G06F17/5077 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/481 ,  H01L23/535 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/045 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01007 ,  H01L2924/01022 ,  H01L2924/00

Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract translation: 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除后侧硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US09301424B2

公开(公告)日：2016-03-29

申请号：US14882658

申请日：2015-10-14

Applicant: International Business Machines Corporation

Inventor： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

IPC: H01L35/00 ,  H05K7/20 ,  H01L23/473

CPC classification number: H05K7/20281 ,  F15D1/0075 ,  F16K99/0032 ,  F16K99/0042 ,  H01L23/34 ,  H01L23/38 ,  H01L23/473 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H05K7/20272 ,  Y10T137/2191

Abstract: A structure and method of using the structure. The structure including an integrated circuit chip having a set of micro-channels; an electro-rheological coolant fluid filling the micro-channels; first and second parallel channel electrodes on opposite sides of at least one micro-channel, the first channel electrode connected to an output of an auto-compensating temperature control circuit, the second channel electrode connected to ground; the auto-compensating temperature control circuit comprising a temperature stable current source connected between a positive voltage rail and the output and having a temperature sensitive circuit connected between ground and the output, a leakage current of the temperature stable current source being essentially insensitive to temperature and a leakage current of the temperature sensitive circuit increasing with temperature.

Abstract translation: 使用该结构的结构和方法。 该结构包括具有一组微通道的集成电路芯片; 填充微通道的电流变冷却液; 在至少一个微通道的相对侧的第一和第二平行通道电极，所述第一通道电极连接到自动补偿温度控制电路的输出，所述第二通道电极连接到地; 所述自动补偿温度控制电路包括连接在正电压轨和所述输出之间的温度稳定电流源，并且具有连接在地和输出之间的温度敏感电路，所述温度稳定电流源的漏电流基本上对温度不敏感， 温度敏感电路的漏电流随温度升高。

公开(公告)号：US20160049353A1

公开(公告)日：2016-02-18

申请号：US14924256

申请日：2015-10-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

IPC: H01L23/46 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/46 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15159 ,  H01L2924/3011

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in an upper surface of the casing, and forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

Abstract translation: 一种组件，包括集成电路的芯片，包括集成电路的壳体，该集成电路包括多个有源元件，并且包括形成在芯片侧面的上部，形成在芯片的另一侧的下部，以及冷却入口和 用于传送冷却剂的冷却出口，设置在壳体的上表面中，并且形成下部的上部和内侧壁的外侧壁;多个贯通晶片通孔（TWV），用于将芯片的集成电路和 壳体的集成电路和连接到壳体的卡，用于将壳体电连接到系统板。

公开(公告)号：US09257366B2

公开(公告)日：2016-02-09

申请号：US14068056

申请日：2013-10-31

Applicant: International Business Machines Corporation

Inventor： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

IPC: H01L35/00 ,  H01L23/473 ,  F16K99/00 ,  F15D1/00

CPC classification number: H05K7/20281 ,  F15D1/0075 ,  F16K99/0032 ,  F16K99/0042 ,  H01L23/34 ,  H01L23/38 ,  H01L23/473 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H05K7/20272 ,  Y10T137/2191

Abstract: A structure and method of using the structure. The structure including an integrated circuit chip having a set of micro-channels; an electro-rheological coolant fluid filling the micro-channels; first and second parallel channel electrodes on opposite sides of at least one micro-channel, the first channel electrode connected to an output of an auto-compensating temperature control circuit, the second channel electrode connected to ground; the auto-compensating temperature control circuit comprising a temperature stable current source connected between a positive voltage rail and the output and having a temperature sensitive circuit connected between ground and the output, a leakage current of the temperature stable current source being essentially insensitive to temperature and a leakage current of the temperature sensitive circuit increasing with temperature.

公开(公告)号：US09082875B2

公开(公告)日：2015-07-14

申请号：US13647538

申请日：2012-10-09

Applicant: International Business Machines Corporation

Inventor： Bruce Balch ,  Kerry Bernstein ,  John Joseph Ellis-Monaghan ,  Nazmul Habib

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor.

Abstract translation: 一种在半导体器件和归一化应变半导体器件中归一化应变的方法。 该方法包括：形成集成电路的第一和第二场效应晶体管; 在所述第一和第二场效应晶体管上形成应力层，所述应力层在所述第一和第二场效应晶体管的沟道区域中引起应变; 以及在所述第二场效应晶体管的至少一部分上选择性地稀薄所述应力层。

公开(公告)号：US20140084443A1

公开(公告)日：2014-03-27

申请号：US14096729

申请日：2013-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

IPC: H01L23/46 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/46 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15159 ,  H01L2924/3011

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

Abstract translation: 一种组件，包括集成电路的芯片，包括集成电路的壳体，该集成电路包括多个有源元件，并且具有形成在芯片的另一侧的芯片侧的上部和形成在芯片的另一侧的下部，多个贯通晶片通孔（TWV ），用于将芯片的集成电路与壳体的集成电路电连接，以及连接到壳体的卡，用于将壳体电连接到系统板。

公开(公告)号：US20140077871A1

公开(公告)日：2014-03-20

申请号：US13621949

申请日：2012-09-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kerry Bernstein

IPC: G05F3/02

CPC classification number: G06F1/26

Abstract: System and method system for regulating voltage in a portion of an integrated circuit. An integrated circuit has a voltage input and at least a portion that is less than all of the integrated circuit, which requires a local voltage level. A voltage selector establishes a target voltage for the portion. A first comparator compares the target voltage to the local voltage and generates a pull up control signal when the local voltage is below the target voltage. A second comparator compares the target voltage to the local voltage and generates a pull down control signal when the local voltage is above the target voltage. A pull up device, responsive to the pull up control signal, increases the local voltage according to the pull up control signal. A pull down device, responsive to the pull down control signal, decreases the local voltage level according to the pull down control signal.

Abstract translation: 用于调整集成电路部分电压的系统和方法系统。 集成电路具有电压输入和小于所有集成电路的至少一部分，其需要局部电压电平。 电压选择器为该部分建立目标电压。 第一个比较器将目标电压与局部电压进行比较，并在局部电压低于目标电压时产生上拉控制信号。 第二比较器将目标电压与局部电压进行比较，并且当局部电压高于目标电压时产生下拉控制信号。 根据上拉控制信号，上拉装置根据上拉控制信号增加局部电压。 根据下拉控制信号，下拉装置根据下拉控制信号降低局部电压电平。