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    POWER MANAGEMENT FOR A COMPUTER SYSTEM
    11.
    发明申请
    POWER MANAGEMENT FOR A COMPUTER SYSTEM 有权
    电脑系统电源管理

    公开(公告)号：US20140281605A1

    公开(公告)日：2014-09-18

    申请号：US13837655

    申请日：2013-03-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Pradip Bose ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

    IPC: G06F1/32

    CPC classification number: G06F1/3243 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3278 ,  G06F3/0656 ,  G06F9/3877 ,  G06F9/44 ,  G06F9/4893 ,  G06F13/00 ,  G06F13/1663 ,  G06F2212/312 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

    Abstract: Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section.

    Abstract translation: 实施例包括一种用于管理计算机系统中的电力的方法，所述计算机系统包括主处理器和包括供电单元的主动存储器设备，所述主存储器设备通过存储器链路与主处理器通信，所述动力单元包括处理元件。 该方法包括主处理器在程序线程上执行程序，遇到要由有源存储器件执行的代码的第一部分，通过第一命令改变有源存储器件上的供电单元的功率状态，基于 主处理器遇到第一部分代码，第一个命令包括一个存储命令。 该方法还包括处理元件在第二时间执行代码的第一部分，基于执行第一部分的处理元件，将主处理器的功率状态从功率使用状态改变到省电状态。

    SEQUENTIAL LOCATION ACCESSES IN AN ACTIVE MEMORY DEVICE
    12.
    发明申请
    SEQUENTIAL LOCATION ACCESSES IN AN ACTIVE MEMORY DEVICE 有权
    有源存储器件中的顺序位置访问

    公开(公告)号：US20140173224A1

    公开(公告)日：2014-06-19

    申请号：US13714724

    申请日：2012-12-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

    IPC: G06F12/00

    CPC classification number: G06F12/00 ,  G06F9/3877 ,  G06F11/00 ,  G06F13/00 ,  G06F15/785

    Abstract: Embodiments relate to sequential location accesses in an active memory device that includes memory and a processing element. An aspect includes a method for sequential location accesses that includes receiving from the memory a first group of data values associated with a queue entry at the processing element. A tag value associated with the queue entry and specifying a position from which to extract a first subset of the data values is read. The queue entry is populated with the first subset of the data values starting at the position specified by the tag value. The processing element determines whether a second subset of the data values in the first group of data values is associated with a subsequent queue entry, and populates a portion of the subsequent queue entry with the second subset of the data values.

    Abstract translation: 实施例涉及包括存储器和处理元件的有源存储器设备中的顺序位置访问。 一个方面包括用于顺序位置访问的方法，其包括从存储器接收与处理元件上的队列条目相关联的第一组数据值。 读取与队列条目相关联并且指定提取数据值的第一子集的位置的标签值。 队列条目用从标签值指定的位置开始的数据值的第一个子集填充。 处理元件确定第一组数据值中的数据值的第二子集是否与后续的队列条目相关联，并且用数据值的第二子集填充后续队列条目的一部分。

    POWER-CONSTRAINED COMPILER CODE GENERATION AND SCHEDULING OF WORK IN A HETEROGENEOUS PROCESSING SYSTEM
    13.
    发明申请
    POWER-CONSTRAINED COMPILER CODE GENERATION AND SCHEDULING OF WORK IN A HETEROGENEOUS PROCESSING SYSTEM 有权
    功率约束编译器代码生成和调度在异构处理系统中的工作

    公开(公告)号：US20140136857A1

    公开(公告)日：2014-05-15

    申请号：US13674224

    申请日：2012-11-12

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hans M. Jacobson ,  Ravi Nair ,  John K.P. O'Brien ,  Zehra N. Sura

    IPC: G06F1/26

    CPC classification number: G06F9/5094 ,  G06F1/329 ,  G06F8/41 ,  G06F9/46 ,  G06F9/4893 ,  Y02D10/24

    Abstract: A heterogeneous processing system includes a compiler for performing power-constrained code generation and scheduling of work in the heterogeneous processing system. The compiler produces source code that is executable by a computer. The compiler performs a method. The method includes dividing a power budget for the heterogeneous processing system into a discrete number of power tokens. Each of the power tokens has an equal value of units of power. The method also includes determining a power requirement for executing a code segment on a processing element of the heterogeneous processing system. The determining is based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, at least one of the power tokens to satisfy the power requirement.

    Abstract translation: 异构处理系统包括用于在异构处理系统中执行功率约束代码生成和调度工作的编译器。 编译器生成可由计算机执行的源代码。 编译器执行一个方法。 该方法包括将异构处理系统的功率预算分成离散数量的功率令牌。 每个功率令牌具有相等的功率单位。 该方法还包括确定在异构处理系统的处理元件上执行代码段的功率需求。 该确定基于处理元件和代码段的特性。 该方法还包括在运行时向处理元件分配至少一个功率令牌以满足功率需求。

    ADDRESS GENERATION IN AN ACTIVE MEMORY DEVICE
    14.
    发明申请
    ADDRESS GENERATION IN AN ACTIVE MEMORY DEVICE 有权
    主动存储器件中的地址生成

    公开(公告)号：US20140129799A1

    公开(公告)日：2014-05-08

    申请号：US13671679

    申请日：2012-11-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

    IPC: G06F12/10

    CPC classification number: G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  Y02D10/13

    Abstract: Embodiments relate to address generation in an active memory device that includes memory and a processing element. An aspect includes a method for address generation in the active memory device. The method includes reading a base address value and an offset address value from a register file group of the processing element. The processing element determines a virtual address based on the base address value and the offset address value. The processing element translates the virtual address into a physical address and accesses a location in the memory based on the physical address.

    Abstract translation: 实施例涉及包括存储器和处理元件的有源存储器件中的地址生成。 一方面包括在活动存储设备中产生地址的方法。 该方法包括从处理元件的寄存器文件组读取基地址值和偏移地址值。 处理元件根据基地址值和偏移地址值确定虚拟地址。 处理元件将虚拟地址转换为物理地址，并基于物理地址访问存储器中的位置。

    Hybrid model for short text classification with imbalanced data
    17.
    发明授权
    Hybrid model for short text classification with imbalanced data 有权

    公开(公告)号：US11328221B2

    公开(公告)日：2022-05-10

    申请号：US16379192

    申请日：2019-04-09

    Applicant: International Business Machines Corporation

    Inventor： Yang Yu ,  Ming Tan ,  Ravi Nair ,  Haoyu Wang ,  Saloni Potdar

    IPC: G06F15/16 ,  G06N20/00 ,  G06F16/35

    Abstract: A method of text classification includes generating a text embedding vector representing a text sample and applying weights of a regression layer to the text embedding vector to generate a first data model output vector. The method also includes generating a plurality of prototype embedding vectors associated with a respective classification labels and comparing the plurality of prototype embedding vectors to the text embedding vector to generate a second data model output vector. The method further includes assigning a particular classification label to the text sample based on the first data model output vector, the second data model output vector, and one or more weighting values.

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