公开(公告)号：US20230282748A1

公开(公告)日：2023-09-07

申请号：US17653476

申请日：2022-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shogo Mochizuki ,  Su Chen Fan ,  Nicolas Jean Loubet ,  Xuan Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/28568 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor structure includes a plurality of nanosheet (NS) channel layers having a plurality of source/drain (S/D) regions on sidewalls thereof; and a continuous contact via being in direct contact with the plurality of S/D regions, wherein the continuous contact via has a substantially same horizontal distance to each of the plurality of NS channel layers. A method of manufacturing the same is also provided.

公开(公告)号：US20230187551A1

公开(公告)日：2023-06-15

申请号：US17551309

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Shogo Mochizuki ,  Juntao Li

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/786 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L23/528

CPC classification number: H01L29/7848 ,  H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L23/5286

Abstract: A device comprises a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is disposed between the first and second interconnect structures. The stacked complementary transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type. The first contact connects a first source/drain element of the first transistor to the first interconnect structure. The second contact connects a first source/drain element of the second transistor to the second interconnect structure. The first and second contacts are disposed in alignment with each other.

公开(公告)号：US20230088757A1

公开(公告)日：2023-03-23

申请号：US17483216

申请日：2021-09-23

Applicant: International Business Machines Corporation

Inventor： Nicolas Loubet ,  Shogo Mochizuki ,  Kirsten Emilie Moselund ,  Cezar Bogdan Zota

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of epitaxial source/drain regions connected to the plurality of channel layers. The plurality of channel layers are connected to the plurality of epitaxial source/drain regions via a plurality of epitaxial extension regions. Respective pairs of adjacent channel layers of the plurality of channel layers are connected to a given one of the plurality of epitaxial source/drain regions via respective ones of the plurality of epitaxial extension regions.

公开(公告)号：US20230072305A1

公开(公告)日：2023-03-09

申请号：US17470686

申请日：2021-09-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki ,  Choonghyun Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66

Abstract: VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.

公开(公告)号：US11562906B2

公开(公告)日：2023-01-24

申请号：US16265784

申请日：2019-02-01

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L21/285 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US11355649B2

公开(公告)日：2022-06-07

申请号：US17136160

申请日：2020-12-29

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) having a nanosheet stack formed over a substrate. The nanosheet stack includes a plurality of channel nanosheets, wherein the plurality of channel nanosheets includes a first channel nanosheet having a first end region, a second end region, and a central region positioned between the first end region and the second end region. The first end region and the second end region include a first type of semiconductor material, wherein, when the first type of semiconductor material is at a first temperature, the first type of semiconductor material has a first diffusion coefficient for a dopant. The central region includes a second type of semiconductor material, wherein, when the second type of semiconductor material is at the first temperature, the second type of semiconductor material has a second diffusion coefficient for the dopant.

公开(公告)号：US20220173240A1

公开(公告)日：2022-06-02

申请号：US17671080

申请日：2022-02-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Shogo Mochizuki ,  Gen Tsutsui ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/24

Abstract: A method of forming a vertical transport fin field effect transistor device is provided. The method includes forming vertical fins on a substrate, depositing a protective liner on the sidewalls of the vertical fins, and removing a portion of the substrate to form a support pillar beneath at least one of the vertical fins. The method further includes etching a cavity in the support pillar of the at least one of the vertical fins, and removing an additional portion of the substrate to form a plinth beneath the support pillar of the vertical fin. The method further includes growing a bottom source/drain layer on the substrate adjacent to the plinth, and forming a diffusion plug in the cavity, wherein the diffusion plug is configured to block diffusion of dopants from the bottom source/drain layer above a necked region in the support pillar.

公开(公告)号：US11316015B2

公开(公告)日：2022-04-26

申请号：US17134731

申请日：2020-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shogo Mochizuki ,  Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li

IPC: H01L29/76 ,  H01L29/161 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L21/768 ,  H01L21/3065 ,  H01L29/49

Abstract: A method for forming the semiconductor device that includes forming an etch mask covering a drain side of the gate structure and the silicon containing fin structure; etching a source side of the silicon containing fin structure adjacent to the channel region; and forming a germanium containing semiconductor material on an etched sidewall of the silicon containing fin structure adjacent to the channel region. Germanium from the germanium containing semiconductor material is diffused into the channel region to provide a graded silicon germanium region in the channel region having germanium present at a highest concentration in the channel region at the source end of the channel region and a germanium deficient concentration at the drain end of the channel region.

公开(公告)号：US11276781B2

公开(公告)日：2022-03-15

申请号：US16849101

申请日：2020-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Shogo Mochizuki ,  Gen Tsutsui ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/24

Abstract: A method of forming a vertical transport fin field effect transistor device is provided. The method includes forming vertical fins on a substrate, depositing a protective liner on the sidewalls of the vertical fins, and removing a portion of the substrate to form a support pillar beneath at least one of the vertical fins. The method further includes etching a cavity in the support pillar of the at least one of the vertical fins, and removing an additional portion of the substrate to form a plinth beneath the support pillar of the vertical fin. The method further includes growing a bottom source/drain layer on the substrate adjacent to the plinth, and forming a diffusion plug in the cavity, wherein the diffusion plug is configured to block diffusion of dopants from the bottom source/drain layer above a necked region in the support pillar.

公开(公告)号：US11257934B2

公开(公告)日：2022-02-22

申请号：US16752817

申请日：2020-01-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  ChoongHyun Lee ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L21/225 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.