公开(公告)号：US11361987B2

公开(公告)日：2022-06-14

申请号：US16874658

申请日：2020-05-14

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saumya Sharma ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for making a semiconductor apparatus includes forming a first bottom interconnect in a device area of a first dielectric layer; fabricating a device on top of the first bottom interconnect; capping the device with a first interlayer dielectric; exposing a logic area of the first dielectric layer that is adjacent to the device area by removing a portion of the first interlayer dielectric from the first dielectric layer while leaving another portion of the first interlayer dielectric that caps the device; and forming a second bottom interconnect in the logic area of the first dielectric layer. By forming the second bottom interconnect after the device fabrication and capping, damage to the device and to the second bottom interconnect is avoided.

公开(公告)号：US11227997B1

公开(公告)日：2022-01-18

申请号：US16922049

申请日：2020-07-07

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saumya Sharma ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L45/00 ,  H01L27/24

Abstract: Embodiments of the present invention are directed to forming a planar Resistive Random Access Memory (RRAM) device with a shared top electrode. In a non-limiting embodiment of the invention, a first trench having a first width and a second trench having a second width less than the first width are formed in a dielectric layer. A bottom liner is formed on sidewalls of the first trench. The bottom liner pinches off the second trench. A top liner is formed on sidewalls of the bottom liner in the first trench. The top liner is formed such that a portion of the bottom liner at a bottommost region of the first trench remains exposed. The exposed portion of the bottom liner is removed, and a memory cell material is formed in the first trench.

公开(公告)号：US20220013723A1

公开(公告)日：2022-01-13

申请号：US16922049

申请日：2020-07-07

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saumya Sharma ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L45/00 ,  H01L27/24

Abstract: Embodiments of the present invention are directed to forming a planar Resistive Random Access Memory (RRAM) device with a shared top electrode. In a non-limiting embodiment of the invention, a first trench having a first width and a second trench having a second width less than the first width are formed in a dielectric layer. A bottom liner is formed on sidewalls of the first trench. The bottom liner pinches off the second trench. A top liner is formed on sidewalls of the bottom liner in the first trench. The top liner is formed such that a portion of the bottom liner at a bottommost region of the first trench remains exposed. The exposed portion of the bottom liner is removed, and a memory cell material is formed in the first trench.

公开(公告)号：US11944013B2

公开(公告)日：2024-03-26

申请号：US17447937

申请日：2021-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Dimitri Houssameddine ,  Huai Huang ,  Tianji Zhou

IPC: H10N50/01 ,  G11C11/16 ,  H01L21/768 ,  H01L23/522 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/01 ,  G11C11/161 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/5226 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, and a magnetic tunnel junction (MTJ) stack aligned above the via. A first back end of line (BEOL) layer including a BEOL dielectric layer surrounding a BEOL metal layer, a second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, a magnetic tunnel junction (MTJ) stack aligned above the via. Forming a via dielectric layer as a second back end of line (BEOL) layer, an opening, a lower metal stud in the opening, a liner on the lower metal stud and on exposed side surfaces of the opening, an upper metal stud in remaining portions of the opening, and forming a magnetic tunnel junction (MTJ) stack aligned above.

公开(公告)号：US20230091345A1

公开(公告)日：2023-03-23

申请号：US17447937

申请日：2021-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Dimitri Houssameddine ,  Huai Huang ,  Tianji Zhou

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L21/768 ,  H01L23/522

Abstract: A second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, and a magnetic tunnel junction (MTJ) stack aligned above the via. A first back end of line (BEOL) layer including a BEOL dielectric layer surrounding a BEOL metal layer, a second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, a magnetic tunnel junction (MTJ) stack aligned above the via. Forming a via dielectric layer as a second back end of line (BEOL) layer, an opening, a lower metal stud in the opening, a liner on the lower metal stud and on exposed side surfaces of the opening, an upper metal stud in remaining portions of the opening, and forming a magnetic tunnel junction (MTJ) stack aligned above.

公开(公告)号：US20210391256A1

公开(公告)日：2021-12-16

申请号：US16903213

申请日：2020-06-16

Applicant: International Business Machines Corporation

Inventor： Tianji Zhou ,  Saumya Sharma ,  Ashim DUTTA ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  G11C17/18 ,  G11C17/16

Abstract: E-fuses and techniques for fabrication thereof using dielectric zipping are provided. An e-fuse device includes: a first dielectric layer disposed on a substrate; at least one first electrode of the e-fuse device present in the first dielectric layer; a second dielectric layer disposed on the first dielectric layer; vias present in the second dielectric layer, wherein at least one of the vias is present over the at least one first electrode and has a critical dimension CDA″, wherein the vias adjacent to the at least one via having the critical dimension CDA″ each have a critical dimension of CDB″, and wherein CDB″>CDA″; a liner disposed in each of the vias; and a metal that serves as a second electrode of the e-fuse device disposed in each of the vias over the liner. A method of operating an e-fuse device is also provided.

公开(公告)号：US20210375986A1

公开(公告)日：2021-12-02

申请号：US16886830

申请日：2020-05-29

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saumya Sharma ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A technique relates to an integrated circuit (IC). Pillars of a set of memory elements are formed. A bilayer dielectric is formed between the pillars, the bilayer dielectric having an upper dielectric material formed on a lower dielectric material without requiring an etch of the lower dielectric material prior to forming the upper dielectric material, thereby preventing a void in the bilayer dielectric, the lower dielectric material including one or more flowable dielectric materials.

公开(公告)号：US20210358801A1

公开(公告)日：2021-11-18

申请号：US16874658

申请日：2020-05-14

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saumya Sharma ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for making a semiconductor apparatus includes forming a first bottom interconnect in a device area of a first dielectric layer; fabricating a device on top of the first bottom interconnect; capping the device with a first interlayer dielectric; exposing a logic area of the first dielectric layer that is adjacent to the device area by removing a portion of the first interlayer dielectric from the first dielectric layer while leaving another portion of the first interlayer dielectric that caps the device; and forming a second bottom interconnect in the logic area of the first dielectric layer. By forming the second bottom interconnect after the device fabrication and capping, damage to the device and to the second bottom interconnect is avoided.

公开(公告)号：US20210233843A1

公开(公告)日：2021-07-29

申请号：US16774922

申请日：2020-01-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chih-Chao Yang ,  Baozhen Li ,  Tianji Zhou ,  Ashim Dutta ,  Saumya Sharma

IPC: H01L23/525 ,  H01L23/522 ,  H01L21/768

Abstract: An anti-fuse device having enhanced programming efficiency is provided. The anti-fuse device includes via contact structures that have different critical dimensions located between a first electrode and a second electrode. Notably, a first via contact structure having a first critical dimension is provided between a pair of second via contact structures having a second critical dimension that is greater than the first critical dimension. When a voltage is applied to the device, dielectric breakdown will occur first through the first via contact structure having the first critical dimension.